LM26003MH NSC [National Semiconductor], LM26003MH Datasheet - Page 10

• Manufacturer Part Number: LM26003MH
• Description: 3A Switching Regulator with High Efficiency Sleep Mode
• Manufacturer: NSC [National Semiconductor]

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the operating frequency can be reduced to increase the nom-
inal on-time. Second, the inductor value can be increased to
slow the current ramp and reduce the peak over-current.
FREQUENCY ADJUSTMENT AND SYNCHRONIZATION
The switching frequency of the LM26003 can be adjusted be-
tween 150 kHz and 500 kHz using a single external resistor.
This resistor is connected from the FREQ pin to ground as
shown in the typical application. The resistor value can be
calculated with the following empirically derived equation:
The switching frequency can also be synchronized to an ex-
ternal clock signal using the SYNC pin. The SYNC pin allows
the operating frequency to be varied above and below the
nominal frequency setting. The adjustment range is from 30%
above nominal to 20% below nominal. External synchroniza-
tion requires a 1.23V minimum (typical) peak signal level at
the SYNC pin. The FREQ resistor must always be connected
to initialize the nominal operating frequency. The operating
frequency is synchronized to the falling edge of the SYNC
input. When SYNC goes low, the high-side switch turns on.
This allows any duty-cycle to be used for the sync signal when
synchronizing to a frequency higher than nominal. When syn-
chronizing to a lower frequency, however, there is a minimum
duty-cycle requirement for the SYNC signal, given in the
equation below:
Where fnom is the nominal switching frequency set by the
FREQ resistor, and fsync is a square wave. If the SYNC pin
is not used, it must be pulled low for normal operation. A 10
kΩ pull-down resistor is recommended to protect against a
missing sync signal. Although the LM26003 is designed to
operate at up to 500 kHz, maximum load current may be lim-
ited at higher frequencies due to increased temperature rise.
See the Thermal Considerations section.
FIGURE 5. Switching Frequency vs R
R
FREQ
= (6.25 x 10
10
) x f
SW
-1.042
FREQ
30067612
10
VBIAS
The VBIAS pin is used to bypass the internal regulator which
provides the bias voltage to the LM26003. When the VBIAS
pin is connected to a voltage greater than 3V, the internal
regulator automatically switches over to the VBIAS input. This
reduces the current into VIN (Iq) and increases system effi-
ciency. Using the VBIAS pin has the added benefit of reducing
power dissipation within the device.
For most applications where 3V < Vout < 10V, VBIAS can be
connected to VOUT. If not used, VBIAS should be tied to
GND.
If VBIAS drops below 2.9V (typical), the device automatically
switches over to supply the internal bias voltage from Vin.
Total device input current is the sum of Iq, gate drive current,
and VBIAS current, plus some negligible current into the FB
pin. Total minimum input supply current can be calculated as
shown below:
Where I
Total supply input current varies according to load, system
efficiency, and operating frequency. To calculate minimum
input current during sleep mode, use Iq
I
For input current in PWM mode, use the same equation, with
Iq
If VBIAS is connected to ground, use the same equation with
the Ibias term eliminated and either Iq
When the LM26003 is powered with the circuit's output volt-
age through VBIAS, especially at low output voltages such as
3.3V, output ripple noise can couple in through the Vbias pin
causing some falling edge jitter on the switch node. To avoid
this, additional bypassing close to the VBIAS pin with a low
ESR capacitor can be implemented. The circuit diagram in
Figure 7 shows this bypass capacitor C8.
LOW VIN OPERATION AND UVLO
The LM26003 is designed to remain operational during short
line transients when input voltage may drop as low as 3.0V.
Minimum nominal operating input voltage is 4.0V. Below this
voltage, switch R
voltage from VDD. The minimum voltage required at VDD is
approximately 3.5V for normal operation within specification.
VDD can also be used as a pull-up voltage for functions such
as PGOOD and FPWM. Note that if VDD is used externally,
the pin is not recommended for loads greater than 1 mA.
If the input voltage approaches the nominal output voltage,
the duty-cycle is maximized to hold up the output voltage. In
this mode of operation, once the duty-cycle reaches its max-
imum, the LM26003 can skip a maximum of seven off pulses,
effectively increasing the duty-cycle and thus minimizing the
dropout from input to output. Typical off-pulse skipping wave-
forms are shown below.
BIAS_SLEEP
PWM_VB
QG
, and I
.
is the gate drive current, calculated as:
BIAS_PWM
DS(ON)
I
QG
= (9.2 x 10
increases, due to the lower gate drive
.
-9
) x f
Sleep_VDD
SW
Sleep_VB
or Iq
PWM_VDD
, and
.