LM26003MH NSC [National Semiconductor], LM26003MH Datasheet - Page 15

• Manufacturer Part Number: LM26003MH
• Description: 3A Switching Regulator with High Efficiency Sleep Mode
• Manufacturer: NSC [National Semiconductor]

A ceramic input capacitor must be connected as close as
possible to the AVIN pin as well as PVIN pin. The capacitor
between AVIN and ground should be grounded close to the
GND pins of the LM26003 and the PVIN capacitor should be
grounded close to the Schottky diode ground. Often, the AVIN
bypass capacitor is most easily located on the bottom side of
the PCB. It increases trace inductance due to the vias, it re-
duces trace length however.
The above layout recommendations are illustrated below in
Figure 11.
It is a good practice to connect the EP, GND pin, and small
signal components (COMP, FB, FREQ) to a separate ground
plane, shown in Figure 11 as EP GND, and in the schematics
as a signal ground symbol. Both the exposed pad and the
GND pin must be connected to ground. This quieter plane
should be connected to the high current ground plane at a
quiet location, preferably near the Vout ground as shown by
the dashed line in Figure 11.
The EP GND plane should be made as large as possible,
since it is also used for thermal dissipation. Several vias can
be placed directly below the EP to increase heat flow to other
layers when they are available. The recommended via hole
diameter is 0.3mm.
The trace from the FB pin to the resistor divider should be
short and the entire feedback trace must be kept away from
FIGURE 11. Example PCB Layout
30067632
15
the inductor and switch node. See Application Note AN-1229
for more information regarding PCB layout for switching reg-
ulators.
Thermal Considerations and TSD
Although the LM26003 has a built in current limit, at ambient
temperatures above 80°C, device temperature rise may limit
the actual maximum load current. Therefore, temperature rise
must be taken into consideration to determine the maximum
allowable load current.
Temperature rise is a function of the power dissipation within
the device. The following equations can be used to calculate
power dissipation (PD) and temperature rise, where total PD
is the sum of FET switching losses, FET DC losses, drive
losses, Iq, and VBIAS losses:
Given this total power dissipation, junction temperature can
be calculated as follows:
Where θ
with a large copper plane area. θ
metallization area.
To calculate the maximum allowable power dissipation, as-
sume Tj = 125°C. To ensure that junction temperature does
not exceed the maximum operating rating of 125°C, power
dissipation should be verified at the maximum expected op-
erating frequency, maximum ambient temperature, and min-
imum and maximum input voltage. The calculated maximum
load current is based on continuous operation and may be
exceeded during transient conditions.
If the power dissipation remains above the maximum allow-
able level, device temperature will continue to rise. When the
junction temperature exceeds its maximum, the LM26003 en-
gages Thermal Shut Down (TSD). In TSD, the part remains
in a shutdown state until the junction temperature falls to with-
in normal operating limits. At this point, the device restarts in
soft-start mode.
Psw
PD
JA
TOTAL
DC
= 32°C/W (typically) when using a multi-layer board
= D x Iload
= Psw
P
Tj = Ta + (PD
QG
P
VBIAS
AC
= Vin x 9.2 x 10
2
P
+ Psw
x (0.095 + 0.00065 x (T
Iq
= Vbias x I
= Vin x Iq
DC
TOTAL
JA
+ PQG + P
varies with board type and
VBIAS
-9
x θ
x fsw
JA
)
Iq
+ P
www.national.com
j
- 25))
VBIAS