STM8S207C6T3B STMICROELECTRONICS [STMicroelectronics], STM8S207C6T3B Datasheet - Page 48

• Manufacturer Part Number: STM8S207C6T3B
• Description: Performance line, 24 MHz STM8S 8-bit MCU, up to 128 KB Flash
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Option bytes
48/103
Table 13.
Option byte no.
OPT3
OPT4
OPT5
OPT6
OPT7
Option byte description (continued)
LSI_EN: Low speed internal clock enable
IWDG_HW: Independent watchdog
WWDG_HW: Window watchdog activation
WWDG_HALT: Window watchdog reset on halt
EXTCLK: External clock selection
CKAWUSEL: Auto wakeup unit/clock
PRSC[1:0] AWU clock prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
Reserved
WAITSTATE Wait state configuration
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
This configures the stabilisation time.
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
This option configures the number of wait states inserted when reading
from the Flash/data EEPROM memory.
1 wait state is required if f
0: No wait state
1: 1 wait state
Doc ID 14733 Rev 12
CPU
Description
> 16 MHz.
STM8S207xx, STM8S208xx