MCP1725-1502E/MC MICROCHIP [Microchip Technology], MCP1725-1502E/MC Datasheet - Page 18

• Manufacturer Part Number: MCP1725-1502E/MC
• Description: 500 mA, Low Voltage, Low Quiescent Current LDO Regulator
• Manufacturer: MICROCHIP [Microchip Technology]

MCP1725
4.6
The C
delay timing for the power good output, as discussed in
the previous section. By adding a capacitor from the
C
delay can be adjusted from 200 µs (no capacitance on
C
See Section 1.0 “Electrical Characteristics” for
C
Once the power good threshold (rising) has been
reached, the C
to V
PWRGD output will transition high when the C
pin voltage has charged to 0.42V. If the output falls
below the power good threshold limit during the
charging time between 0.0V and 0.42V on the C
pin, the C
thus resetting the timer. The C
until the output voltage of the LDO has once again risen
above the power good rising threshold. A timing
diagram showing C
in
FIGURE 4-4:
Diagram.
DS22026A-page 18
DELAY
DELAY
DELAY
V
Figure
0V
PWRGD
OUT
IN
. The charging current is 140 nA (typical). The
DELAY
) to 300 ms (0.1 µF of capacitance on C
T
timing tolerances.
pin to ground, the PWRGD power-up time
C
PG
4-4.
DELAY
DELAY
input is used to provide the power-up
C
DELAY
DELAY
pin voltage will be pulled to ground,
C
V
DELAY
PWRGD_TH
Input
DELAY
pin charges the external capacitor
C
Threshold (0.42V)
DELAY
, PWRGD and V
V
IN
DELAY
(typ)
and PWRGD Timing
pin will be held low
OUT
is shown
DELAY
DELAY
DELAY
).
4.7
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The typical value of
this shutdown threshold is 30% of V
and maximum limits over the entire operating
temperature range of 45% and 15%, respectively.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
the 30 µs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation value. If
the SHDN input signal is pulled low during the 30 µs
delay period, the timer will be reset and the delay time
will start over again on the next rising edge of the
SHDN input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regulation is
typically 100 µs. See
the SHDN input.
FIGURE 4-5:
Diagram.
V
SHDN
OUT
30 µs
Shutdown Input (SHDN)
T
OR
70 µs
Figure 4-5
Shutdown Input Timing
© 2006 Microchip Technology Inc.
for a timing diagram of
IN
, with minimum
400 ns (typ)