LT3582 LINER [Linear Technology], LT3582 Datasheet - Page 20

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LT3582

Manufacturer Part Number
LT3582
Description
I2C Programmable Boost and Single Inductor Inverting DC/DC Converters with OTP
Manufacturer
LINER [Linear Technology]
Datasheet

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LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
Output Disconnect Operating Limits
The LT3582 series has a PMOS output disconnect switch
connected between CAPP and V
operation, the switch is closed and current is internally
limited to about 155mA (see Figure 9). Make sure that
the output load current doesn’t exceed the PMOS current
limit. Exceeding the current limit causes a signifi cant
rise in PMOS power consumption which may damage
the device.
During shutdown, the PMOS switch is open and CAPP is
isolated from V
In most cases this allows V
However, when the Boost inductor input exceeds 5.5V,
the CAPP-V
current fl ow through the PMOS switch. In addition, apply-
ing CAPP-V
activate internal protection circuitry which turns the PMOS
“on” (see Figure 10). If the current is not limited, this can
lead to a sharp increase in the PMOS power consumption
and may damage the device. If this situation cannot be
avoided, limit PMOS power consumption to less than 1/3
Watt (about 50mA at 7V) to avoid damaging the device.
Refer to the Absolute Maximum Ratings table for maximum
limits on CAPP-V
20
Figure 9: PMOS Current vs. Voltage During Normal Operation
OUTP
OUTP
180
160
140
120
100
80
60
40
20
0
OUTP
0
voltages in excess of 5.7V(typical) may
OUTP
voltage may exceed 5V allowing some
100
up to a voltage difference of 5-5.5V.
voltages and currents.
CAPP-V
200
OUTP
OUTP
300
to discharge to ground.
(mV)
OUTP
400
. During normal
3582512 F10
500
Improving Boost Converter Effi ciency
The effi ciency of the Boost converter can be improved by
shorting the CAPP pin to the V
power loss in the PMOS disconnect circuit is then made
negligible. In most applications, the associated CAPP pin
capacitor can be removed and the larger V
can adequately fi lter the output voltage.
Note that the ripple voltage on V
crease in this confi guration since the output disconnect
PMOS, when not shorted, helps to create an RC fi lter at
the output. Also, if the V
the power-down discharge should not be enabled. V
cannot be discharged to ground during shutdown due to
the path from V
Figure 10: PMOS Current vs. Voltage During Shutdown
I
CAPP-VOUTP
20μA/DIV
13
4
3
2
8
Figure 11: Improved Effi ciency
IN
SWN
SWN
GND
V
SHDN
OUTN
to V
RAMPP
OUTP
V
CAPP-VOUTP
LT3582
7
OUTP
RAMPN
through the external inductor
OUTP
6
1V/DIV
V
CAPP
CAPP
SWP
OUTP
SDA
pin is shorted to CAPP,
SCL
V
V
CA
PP
IN
pin (see Figure 11). The
OUTP
3582512 F12
12
5
11
10
9
14
15
16
1
3582512 F11
will typically in-
OUTP
C1
capacitor
I
LOAD
3582512f
OUTP

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