TEA0675T PHILIPS [NXP Semiconductors], TEA0675T Datasheet - Page 14

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TEA0675T

Manufacturer Part Number
TEA0675T
Description
Dual Dolby* B-type noise reduction circuit for playback applications
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheets

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Description of the principle timing diagram for AMS-latch mode with initial input signal (see Fig.8)
This is similar to the description in Section “Description of
the principle timing diagram for AMS-scan mode with initial
input signal (see Fig.6)”. It only differs in its rise time t
a release of its internal latch when voltage V
upper threshold between t
procedure is completed.
1996 Jun 07
Dual Dolby* B-type noise reduction circuit
for playback applications
handbook, full pagewidth
t r : rise time
t d : delay time
t b : burst time
t p : pause time
t f : fall time
upper threshold
level threshold
time threshold
latch status
to power FET
output signal
(hysteresis)
internal
V AMSEQ
V REF
4.5 V
V in
V t
V l
H
L
0
AMS on
t 0 t 1
and t
1
. Now the initial
t 5 t 6
Fig.8 AMS-latch mode with initial input signal.
t d
t f
t
t 7 t 8 t 9 t 10
passes the
t b t r
r
and
14
t 11 t 12
The following behaviour does not differ from the
description in Section “Description of the principle timing
diagram for AMS-latch mode without initial input signal
(see Fig.7)”.
t 13 t 14
t p t d
t 15
V l : voltage at
pin 3 (CONTRA)
V t : voltage at
pin 22 (CONTRB)
Preliminary specification
level detector
input
time detector
input
MED628
TEA0675
t
t
t
t
t

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