ATMEGA128RFA1_11 ATMEL [ATMEL Corporation], ATMEGA128RFA1_11 Datasheet - Page 158

• Manufacturer Part Number: ATMEGA128RFA1_11
• Description: 8-bit Microcontroller with Low Power 2.4GHz Transceiver for ZigBee and IEEE 802.15.4
• Manufacturer: ATMEL [ATMEL Corporation]

Table 12-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
12.2.1 Idle Mode
158
Sleep Mode
Idle
ADCNRM
Power-down
Power-save
Standby
Extended
Standby
(1)
ATmega128RFA1
Active Clock Domains
X
To enter any of the sleep modes, the SE bit in in the SMCR register (see
Sleep Mode Control Register" on page
instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register
select which sleep mode will be activated by the SLEEP instruction. See chapter
"Register Description" on
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up.
The MCU is then halted for four cycles in addition to the start-up time, executes the
interrupt routine, and resumes execution from the instruction following SLEEP. The
contents of the Register File and SRAM are unaltered when the device wakes up from
sleep. Note that SRAM data retention must be enabled in some sleep modes to
preserve the memory contents (see section
If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset
Vector.
When the SM2:0 bits are written to 000 in the SMCR register, the SLEEP instruction
makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART,
Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts clk
clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and
Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC
is enabled, a conversion starts automatically when this mode is entered.
Notes:
FLASH
X
X
, while allowing the other clocks to run.
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT7:4, only level interrupt.
4. The Symbol Counter and/or the Transceiver can wakeup the AVR if the
X
X
X
X
(2)
Transceiver Oscillator is enabled (Transceiver not in SLEEP).
Oscillators
X
X
X
X
X
X
X
X
page 168 for a summary.
(2)
(2)
(2)
(2)
X
X
X
X
X
X
(3)
(3)
(3)
(3)
(3)
X
X
X
X
X
X
168) must be written to logic one and a SLEEP
"SRAM with Data Retention" on
X
X
X
X
(2)
Wake-up Sources
X
X
X
X
X
X
X
X
X
X
8266C-MCU Wireless-08/11
X
page 164).
"SMCR –
X
X
X
X
X
X
CPU
(4)
(4)
(4)
(4)
(4)
(4)
and
X
X
X
X
X
X
(4)
(4)
(4)
(4)
(4)
(4)