ATMEGA128RFA1_11 ATMEL [ATMEL Corporation], ATMEGA128RFA1_11 Datasheet - Page 343

• Manufacturer Part Number: ATMEGA128RFA1_11
• Description: 8-bit Microcontroller with Low Power 2.4GHz Transceiver for ZigBee and IEEE 802.15.4
• Manufacturer: ATMEL [ATMEL Corporation]

23.3.2 Double Speed Operation (U2Xn)
23.3.3 External Clock
23.3.4 Synchronous Clock Operation
8266C-MCU Wireless-08/11
BAUD
f
UBRRn
Some examples of UBRRn values for some system clock frequencies are found in
Table 23-14 on page
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit
only has effect for the asynchronous operation. Set this bit to zero when using
synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively
doubling the transfer rate for asynchronous communication. Note however that the
receiver will in this case only use half the number of samples (reduced from 16 to 8) for
data sampling and clock recovery, and therefore a more accurate baud rate setting and
system clock are required when this mode is used. For the transmitter, there are no
downsides.
External clocking is used by the synchronous slave modes of operation. The description
in this section refers to
External clock input from the XCKn pin is sampled by a synchronization register to
minimize the chance of meta-stability. The output from the synchronization register
must then pass through an edge detector before it can be used by the transmitter and
receiver. This process introduces a two CPU clock period delay and therefore the
maximum external XCKn clock frequency is limited by the following equation:
Note that f
recommended to add some margin to avoid possible loss of data due to frequency
variations.
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either
clock input (slave) or clock output (master). The dependency between the clock edges
and data sampling or data change is the same. The basic principle is that data input (on
RxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn)
is changed.
OSC
Operating Mode
Synchronous Master Mode
Note:
1. The baud rate is defined to be the transfer rate in bit per second (bps).
OSC
depends on the stability of the system clock source. It is therefore
Baud rate (in bits per second, bps)
System oscillator clock frequency
Contents of the UBRRHn and UBRRLn registers, (0-4095)
366.
Figure 22-2 on
Equation for Calculating
Baud Rate
BAUD
f
page 332 for details.
=
XCK
(1)
( 2
UBRRn
<
f
f
OSC
OSC
4
+
ATmega128RFA1
) 1
Equation for Calculating
UBRR Value
UBRRn
=
2
BAUD
f
OSC
−
1
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