P87C654X2 PHILIPS [NXP Semiconductors], P87C654X2 Datasheet
P87C654X2
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P87C654X2 Summary of contents
Page 1
... P83C654X2/P87C654X2 80C51 8-bit microcontroller family 16 kB OTP/ROM, 256B RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Product data Supersedes data of 2003 Feb 13 hilips Semiconductors INTEGRATED CIRCUITS 2004 Apr 20 ...
Page 2
... PLCC44 plastic leaded chip carrier; 44 leads LQFP44 plastic low profile quad flat package; 44 leads; body Product data P83C654X2/P87C654X2 = Temp Range ( Version SOT187–2 –40 to +85 SOT389– +70 SOT187–2 –40 to +85 SOT389– ...
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... BYTE DATA RAM PORT 3 CONFIGURABLE I/Os PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os CRYSTAL OR OSCILLATOR RESONATOR 2004 Apr OTP/ROM, ACCELERATED 80C51 CPU (12-CLK MODE, 6-CLK MODE) ENHANCED UART WATCHDOG TIMER 3 Product data P83C654X2/P87C654X2 FULL-DUPLEX TIMER 0 TIMER 1 TIMER 2 2 FAST I C su01728 ...
Page 4
... PORT 0 PORT 2 DRIVERS DRIVERS PORT 0 PORT 2 LATCH LATCH TMP2 TMP1 ALU SFRs TIMERS PSW P.C.A. PORT 1 LATCH PORT 1 DRIVERS P1.0–P1.7 4 Product data P83C654X2/P87C654X2 OTP/ROM MEMORY 8 STACK POINTER PROGRAM ADDRESS REGISTER BUFFER PC INCRE- MENTER 8 16 PROGRAM COUNTER DPTR’S MULTIPLE PORT 3 LATCH PORT 3 DRIVERS P3.0– ...
Page 5
... ALE SS2 35 EA P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 SU01729 and V be SS2 SS3 5 Product data P83C654X2/P87C654X2 LQFP Pin Function Pin Function P0.6/AD6 SS1 1 17 NIC 32 P0.5/AD5 18 P2.0/A8 33 P0.4/AD4 19 P2.1/A9 34 P0.3/AD3 20 P2.2/A10 35 P0 ...
Page 6
... PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. 6 Product data P83C654X2/P87C654X2 ). IL ). Port 2 emits the high-order address byte IL ...
Page 7
... The value on the EA pin is latched when RST is released and any subsequent changes have no effect. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. 7 Product data P83C654X2/P87C654X2 + 0 less than CC ...
Page 8
... SM1 SM2 REN TF1 TR1 TF0 TR0 TF2 EXF2 RCLK TCLK EXEN2 – – – – 8 Product data P83C654X2/P87C654X2 RESET VALUE LSB 00H – – AO xxxx1xx0B GPS 0 – DPS xxxx00x0B 00H – ...
Page 9
... Reset value depends on reset source. 2004 Apr OTP/ROM, BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB GATE C CR2 ENA1 STA STO SC4 SC3 SC2 SC1 9 Product data P83C654X2/P87C654X2 RESET VALUE LSB 00H 00H 00H GATE C 00H SI AA CR1 CR0 00H SC0 0 ...
Page 10
... Figure 1. Clock control (CKCON) register Table 1. OX2 clock mode bit (can only be set by parallel programmer) erased erased programmed 10 Product data P83C654X2/P87C654X2 Reset Value = x0000000B 1 0 – X2 SU01689 X2 bit CPU clock mode (CKCON.0) 0 12-clock mode (default) 1 6-clock mode ...
Page 11
... MHz operating frequency ( MHz in 12-clock mode). To configure the Timer/Counter clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. 11 Product data P83C654X2/P87C654X2 is restored to its normal less than 4 V, but are required for ...
Page 12
... Note, however, that the baud-rate and the Clock-Out frequency will be the same. ALE PSEN PORT Data 1 1 Float 0 0 Data 0 0 Float 12 Product data P83C654X2/P87C654X2 PORT 1 PORT 2 PORT 3 Data Data Data Data Address Data Data Data Data Data Data Data ...
Page 13
... Mode 3, or can still be used by the serial port as a baud rate generator fact, in any application not requiring an interrupt C GATE C/T TIMER 1 TIMER 0 13 Product data P83C654X2/P87C654X2 Reset Value = 00H SU01580 ...
Page 14
... Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Figure 4. Timer/Counter 0/1 Control (TCON) Register 2004 Apr OTP/ROM, C TLn (5 Bits) C Control TF0 TR0 IE1 IT1 14 Product data P83C654X2/P87C654X2 THn TFn Interrupt (8 Bits) SU01618 Reset Value = 00H 1 0 IE0 IT0 SU01516 ...
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... Figure 6. Timer/Counter 0 Mode 3: Two 8-Bit Counters 2004 Apr OTP/ROM, C TLn (8 Bits) C Control THn (8 Bits) C TL0 (8 Bits) C Control TH0 (8 Bits) Control TR1 15 Product data P83C654X2/P87C654X2 TFn Interrupt Reload SU01619 TF0 Interrupt TF1 Interrupt SU01620 ...
Page 16
... TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation. RCLK TCLK EXEN2 TR2 16 Product data P83C654X2/P87C654X2 (LSB) C/T2 CP/RL2 SU01251 ...
Page 17
... Baud rate generator 0 (off) TL2 TH2 (8 BITS) (8 BITS) Control TR2 Capture RCAP2L RCAP2H Figure 8. Timer 2 in Capture Mode — — — — Product data P83C654X2/P87C654X2 MODE TF2 Timer 2 Interrupt EXF2 SU01252 Reset Value = XXXX XX00B T2OE DCEN 1 0 SU00729 ...
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... CONTROL (DOWN COUNTING RELOAD VALUE) FFH FFH OVERFLOW TL2 TH2 CONTROL RCAP2L RCAP2H (UP COUNTING RELOAD VALUE) Figure 11. Timer 2 Auto Reload Mode (DCEN = 1) 18 Product data P83C654X2/P87C654X2 TF2 TIMER 2 INTERRUPT EXF2 SU01253 TOGGLE EXF2 TF2 INTERRUPT COUNT DIRECTION DOWN T2EX PIN ...
Page 19
... EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. 19 Product data P83C654X2/P87C654X2 Timer 1 Overflow 2 “0” “1” ...
Page 20
... Also see Table 6 for set-up of Timer counter. INTERNAL CONTROL (Note 1) 00H 01H 34H 24H 14H INTERNAL CONTROL (Note 1) 02H 03H 20 Product data P83C654X2/P87C654X2 f OSC [65536 * (RCAP2H, RCAP2L)]] [ 6-clock mode 32 in 12-clock mode f OSC n * Baud Rate T2CON EXTERNAL CONTROL ...
Page 21
... TMOD = 0001B), and using the Timer 1 interrupt 16-bit software reload. Figure 14 lists various commonly used baud rates and how they can be obtained from Timer 1. 21 Product data P83C654X2/P87C654X2 (Oscillator Frequency) (Timer 1 Overflow Rate) Oscillator Frequency 12 [256–(TH1)] ...
Page 22
... RECEIVE enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are 22 Product data P83C654X2/P87C654X2 Reset Value = 00H / ...
Page 23
... RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input. 23 Product data P83C654X2/P87C654X2 ...
Page 24
... SBUF Read SBUF 80C51 Internal Bus Figure 15. Serial Port Mode 0 24 Product data P83C654X2/P87C654X2 RxD P3.0 Alt Output Function TxD P3.1 Alt Shift Output Clock Function RxD P3.0 Alt Input Function Transmit D6 D7 ...
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... SBUF RX Control Shift Start 1FFH Bit Detector Input Shift Register (9 Bits) Load SBUF SBUF Read SBUF 80C51 Internal Bus Figure 16. Serial Port Mode 1 25 Product data P83C654X2/P87C654X2 TxD Shift Transmit D7 Stop Bit D7 Stop Bit Receive SU00540 ...
Page 26
... Shift Start 1FFH Bit Detector Input Shift Register (9 Bits) Load SBUF SBUF Read SBUF 80C51 Internal Bus Figure 17. Serial Port Mode 2 26 Product data P83C654X2/P87C654X2 TxD Shift Transmit D7 TB8 Stop Bit D7 RB8 Stop Bit Receive SU00541 ...
Page 27
... Shift Start 1FFH Bit Detector Input Shift Register (9 Bits) Load SBUF SBUF Read SBUF 80C51 Internal Bus Figure 18. Serial Port Mode 3 27 Product data P83C654X2/P87C654X2 TxD Shift Transmit D7 TB8 Stop Bit D7 RB8 Stop Bit Receive SU00542 ...
Page 28
... Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. 28 Product data P83C654X2/P87C654X2 1100 0000 1111 1110 = 1100 000X 1100 0000 ...
Page 29
... POF LVF GF0 Figure 19. UART Framing Error Detection SM0 SM1 SM2 REN COMPARATOR 29 Product data P83C654X2/P87C654X2 ONLY IN STOP MODE 2, 3 BIT SCON TI RI (98H) PCON GF1 IDL (87H) SU00044 D7 D8 SCON TB8 RB8 TI RI ...
Page 30
... If bus arbitration is lost in the master mode, the I immediately and can detect its own slave address in the same serial transfer. 30 Product data P83C654X2/P87C654X2 2 C-bus logic may operate in the 2 C-bus may operate as a master and C-bus hardware looks for its own ...
Page 31
... S1DAT always contains the last byte present on the bus. Thus, in the event of lost arbitration, the transition from master 2 C-bus will respond transmitter to slave receiver is made with the correct data in S1DAT. 31 Product data P83C654X2/P87C654X2 SDA SCL OTHER DEVICE WITH 2 I C-BUS INTERFACE ...
Page 32
... COMPARATOR S1DAT SHIFT REGISTER ARBITRATION & SYNC LOGIC TIMING CONTROL LOGIC SERIAL CLOCK GENERATOR TIMER 1 OVERFLOW S1CON CONTROL REGISTER STATUS BITS STATUS DECODER S1STA STATUS REGISTER 2 C-bus Serial Interface Block Diagram 32 Product data P83C654X2/P87C654X2 8 ACK 8 & OSC INTERRUPT 8 8 su00966 ...
Page 33
... The serial interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is cleared. (1) ( Figure 24. Arbitration Procedure (1) (3) (2) SPACE DURATION Figure 25. Serial Clock Synchronization 33 Product data P83C654X2/P87C654X2 ( ACK SU00967 (1) SU00968 ...
Page 34
... ENS1 = 1: When ENS1 is “1”, I port latches must be set to logic 1. ENS1 should not be used to temporarily release C-bus since, when ENS1 is reset, the I AA flag should be used instead (see description of the AA flag in the following text). 34 Product data P83C654X2/P87C654X2 2 C-bus SD5 ...
Page 35
... In a slave mode, the STO flag may be set to recover from an error condition. In this case, no STOP condition is transmitted to the 2 I C-bus. However, the I has been received and switches to the defined “not addressed” slave receiver mode. The STO flag is automatically cleared by hardware. 35 Product data P83C654X2/P87C654X2 ACK SU00969 D0 A SHIFT IN (2) (2) A (2) ...
Page 36
... A valid status code is present in S1STA one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software. 36 Product data P83C654X2/P87C654X2 2 C-bus while the released from the bus, START C ...
Page 37
... CR0 12 MHz 3. 100 1 0 200 1 7 300 1 1 400 37 Product data P83C654X2/P87C654X2 f DIVIDED BY osc 128 112 96 80 480 (256– (reload value Timer1)) Reload value Timer 1 in Mode 2. f DIVIDED BY osc 256 224 192 160 960 120 ...
Page 38
... While AA is reset general call address. However, the I address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate I 2 the I C-bus Product data P83C654X2/P87C654X2 2 C may switch to the 8EH – – – – Fast/ – – ...
Page 39
... CONTINUES 38H OTHER MST A CONTINUES 68H 78H 80H 39 Product data P83C654X2/P87C654X2 Ç Ç Ç Ç Ç Ç 28H Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç S SLA W Ç Ç Ç Ç Ç Ç Ç ...
Page 40
... CONTINUES TO CORRESPONDING 68H 78H 80H STATES IN SLAVE MODE 2 C-BUS. SEE TABLE 10. 40 Product data P83C654X2/P87C654X2 Ç Ç Ç Ç Ç Ç DATA A P Ç Ç Ç Ç Ç Ç 58H Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...
Page 41
... CALL Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç 70H A 78H 2 C BUS. SEE TABLE 11. 41 Product data P83C654X2/P87C654X2 Ç Ç Ç Ç Ç Ç A DATA SLA Ç Ç Ç Ç Ç Ç 80H 80H A0H Ç ...
Page 42
... AND ADDRESSED AS SLAVE B0H LAST DATA BYTE TRANSMITTED. SWITCHED TO NOT ADDRESSED SLAVE (AA BIT IN S1CON = “0” BUS. SEE TABLE 12. 42 Product data P83C654X2/P87C654X2 Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç DATA Ç Ç Ç ...
Page 43
... Product data P83C654X2/P87C654X2 2 2 NEXT ACTION TAKEN BY AND I C HARDWARE HARDWARE SLA+W will be transmitted; ACK bit will be received As above SLA+W will be transmitted will be switched to MST/REC mode Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted ...
Page 44
... Product data P83C654X2/P87C654X2 2 2 NEXT ACTION TAKEN HARDWARE SLA+R will be transmitted; ACK bit will be received As above SLA+W will be transmitted will be switched to MST/TRX mode 2 I C-bus will be released will enter a slave mode ...
Page 45
... Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. 45 Product data P83C654X2/P87C654X2 2 2 NEXT ACTION TAKEN HARDWARE ...
Page 46
... Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. 46 Product data P83C654X2/P87C654X2 2 2 NEXT ACTION TAKEN HARDWARE 2 2 NEXT ACTION TAKEN HARDWARE ...
Page 47
... STO flag while the STA flag is still set. No STOP condition is transmitted. The STOP condition was received and is able to transmit a START condition. The STO flag is cleared by hardware (see Figure 33). 47 Product data P83C654X2/P87C654X2 2 2 NEXT ACTION TAKEN HARDWARE switched to the not addressed 2 ...
Page 48
... This status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 13 hardware 48 Product data P83C654X2/P87C654X2 SU00975 SU00976 2 C immediately switches to the not addressed ...
Page 49
... Each state routine is part of 2 the I C interrupt routine and handles one of the 26 states. It ends with a RETI instruction which causes a return to the main program. 49 Product data P83C654X2/P87C654X2 (3) SU00977 OUTINE Save PSW Push status code (low order address byte) ...
Page 50
... NUMBER OF BYTES AS MASTER SLA+R TRANSMITTED TO SLA HIGHER ADDRESS BYTE INTERRUPT ROUTINE SLAVE TRANSMITTER DATA RAM SLAVE RECEIVER DATA RAM MASTER RECEIVER DATA RAM MASTER TRANSMITTER DATA RAM Figure 35 Data Memory Map 50 Product data P83C654X2/P87C654X2 CR0 ...
Page 51
... C behaves essentially as a passive device. In the master modes, an internal timer may be used to cause a time-out if a serial transfer is not complete after a defined period of time. This time period is defined by the system connected to the I 51 Product data P83C654X2/P87C654X2 2 C enters the not selected 2 C enters 2 ...
Page 52
... Product data P83C654X2/P87C654X2 ! STA bit in S1CON ! IP0, SI01 Priority bit –0xd5 ! Generates STOP ! (CR0 = 100kHz) –0xc5 ! Releases BUS and ! ACK –0xc1 ! Releases BUS and ! NOT ACK –0xe5 ! Releases BUS and ...
Page 53
... Bus error. st0 0x100 mov S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! clr SI pop psw reti 53 Product data P83C654X2/P87C654X2 ! RESET ! Load own SLA + enable ! general call recognition ! P1.6 High level. ! P1.7 High level. ! Enable SI01 interrupt ! SI01 interrupt low priority ! Initialize SLV funct. ! Transmit 4 bytes. ! SLA+W, Transmit funct. ...
Page 54
... BACKUP,NUMBYTMST pop psw reti : 18, Previous state was STATE 8 or STATE 10, SLA+W have been transmitted, ACK has been received. mts18 0x118 mov psw,#SELRB3 mov S1DAT,@r1 ajmp CON 54 Product data P83C654X2/P87C654X2 ! Load SLA+R/W ! clr SI ! Load SLA+R/W ! clr SI ! Save initial value ...
Page 55
... Arbitration lost in SLA+W or DATA. A new START condition is transmitted when the IIC-bus is free again. mts38 0x138 mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 mov NUMBYTMST,BACKUP ajmp RETmt 55 Product data P83C654X2/P87C654X2 ! set STO, clr SI ! JMP if NOT last DATA ! clr SI, set AA ! clr SI, set AA ! set STO, clr SI ...
Page 56
... RETmr mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 inc r0 pop psw reti : 58, DATA have been received, NOT ACK returned. mrs58 0x158 mov psw,#SELRB3 mov @R0,S1DAT sjmp STOP 56 Product data P83C654X2/P87C654X2 ! clr STA, STO, SI set AA ! set STO, clr SI ! Read received DATA ! clr SI,AA ! clr SI, set AA ...
Page 57
... Arbitration lost in SLA+R/W as MST. General call has been received, ACK returned. STA is set to restart MST mode after the bus is free again. srs78 0x178 mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 mov psw,#SELRB3 ajmp INITSRD 57 Product data P83C654X2/P87C654X2 ! clr SI, set AA ! clr SI, set AA ! Initialize SRD counter ! Initialize SRD counter ...
Page 58
... DATA has been received, NOT ACK has been returned. Recognition of own SLA. General call recognized, if S1ADR. 0–1. srs98 0x198 mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 pop psw reti 58 Product data P83C654X2/P87C654X2 ! Read received DATA ! clr SI,AA ! clr SI, set AA ! clr SI, set AA ! Read received DATA ! clr SI, set AA ...
Page 59
... B0, Arbitration lost in SLA and R/W as MST. Own SLA+R received, ACK returned. STA is set to restart MST mode after the bus is free again. stsb0 0x1b0 mov S1DAT,STD mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 ajmp INITBASE2 59 Product data P83C654X2/P87C654X2 ! clr SI, set AA ! load DATA in S1DAT ! clr SI, set AA ! load DATA in S1DAT ...
Page 60
... C0, DATA has been transmitted, NOT ACK received. stsc0 0x1c0 mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 pop psw reti : C8, Last DATA has been transmitted (AA=0), ACK received. stsc8 0x1c8 mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 pop psw reti 60 Product data P83C654X2/P87C654X2 ! clr SI, set AA ! clr SI, set AA ! clr SI, set AA ...
Page 61
... When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed – ET2 ES ET1 EX1 Figure 36. IE Registers 61 Product data P83C654X2/P87C654X2 INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL IP.x 0 Level 0 (lowest priority) 1 Level 1 0 Level 2 1 Level 3 (highest priority) VECTOR ADDRESS 1 2 ...
Page 62
... IPH.0 PX0H External interrupt 0 priority bit high. 2004 Apr OTP/ROM – PT2 PS PT1 PX1 Figure 37. IP Registers – PT2H PSH PT1H PX1H Figure 38. IPH Registers 62 Product data P83C654X2/P87C654X2 1 0 PT0 PX0 SU01743 1 0 PT0H PX0H SU01744 ...
Page 63
... SFRs. See Application Note AN458 for more details. FF FFFF UPPER SPECIAL FUNCTION REGISTER 80 LOWER 00 0000 63 Product data P83C654X2/P87C654X2 DPTR1 DPTR0 DPH DPL (83H) (82H) EXTERNAL DATA MEMORY SU00745A Figure 39. Increments the data pointer by 1 Loads the DPTR with a 16-bit constant ...
Page 64
... RESET pulse at the reset pin (see note below). The RESET pulse duration 12-clock mode), where T WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. 64 Product data P83C654X2/P87C654X2 (6-clock mode; 196 in osc = 1 make the best use of the osc osc ...
Page 65
... Oscillator frequency CLCL 2004 Apr OTP/ROM, OPERATING MODE POWER SUPPLY VOLTAGE 6-clock 6-clock 2 5.5 V 12-clock 12-clock 2 5 Product data P83C654X2/P87C654X2 RATING UNIT 0 to +70 or –40 to +85 C –65 to +150 +13.0 V –0 1.5 W unless otherwise SS CLOCK FREQUENCY RANGE ...
Page 66
... C to +85 C amb on ALE and PSEN to momentarily fall below the V OH vs. Frequency CC FREQ.[MHz] = – + –750 A. amb TL must be externally limited as follows the voltage specification Product data P83C654X2/P87C654X2 LIMITS UNIT 1 MIN TYP MAX –0.5 0.2V – 0 –0.5 0. –0.5 0.2V – ...
Page 67
... INT0 and INT1 pins. Previous devices provided only an inherent glitch rejection. 12. Power-down mode for 3 V range: Commercial Temperature Range – typ: 0.5 A, max Industrial Temperature Range – typ. 1.0 A, max 2004 Apr OTP/ROM, 67 Product data P83C654X2/P87C654X2 ...
Page 68
... C to +85 C amb 1.2 40 – on ALE and PSEN to momentarily fall below the V OH vs. Frequency. CC FREQ.[MHz] = – + –750 . amb TL must be externally limited as follows the voltage specification Product data P83C654X2/P87C654X2 UNIT 1 TYP MAX 0.2V – ...
Page 69
... CLCL – t – 10 CLCL 0.32t CLCL 0.32t CLCL – – 12t CLCL 10t – 25 CLCL 2t – 15 CLCL 0 5 – 69 Product data P83C654X2/P87C654X2 Unit 16 MHz Clock MAX MIN MAX 33 – – MHz – 117 – ns – 49.5 – ns – 42.5 – – 35 – ...
Page 70
... CLCL – t – 15 CLCL 0.32t CLCL 0.32t CLCL – – 12t CLCL 10t – 25 CLCL 2t – 15 CLCL 0 5 – 70 Product data P83C654X2/P87C654X2 Unit 16 MHz Clock MAX MIN MAX 16 – – MHz – 115 – ns – 47.5 – ns – 37.5 – – 55 – ...
Page 71
... CLCL 3.5t – 5 CLCL – 0.5t – 10 CLCL 0.4t CLCL 0.4t CLCL – – 6t CLCL 5t –25 CLCL t – 15 CLCL 0 6 – 71 Product data P83C654X2/P87C654X2 Unit 16 MHz Clock MAX MIN MAX 30 – – MHz – 54.5 – ns – 18.25 – ns – 11.25 – –35 – CLCL – ...
Page 72
... CLCL 5t –25 – CLCL t – 15 – CLCL 0 – 6 – 5t CLCL 0 100 4.7 – 4.0 – 4.7 – 4.0 – 4.7 – 72 Product data P83C654X2/P87C654X2 Unit 16 MHz Clock MIN MAX – – MHz 52.5 – ns 16.25 – ns 6.25 – ns –55 – 16.25 – ns 78.75 – ns – 55 – 38.75 ns CLCL 0 – ...
Page 73
... Below 16 MHz this parameter is 4t – 133 CLCL 2004 Apr OTP/ROM, 5.0 – 0 – 250 – – 1000 – 300 4.0 – – 400 – – 73 Product data P83C654X2/P87C654X2 s – – 0 0.9 100 – 0.1 c 300 0.1 c 300 ns b 0.6 – s – 400 pF ...
Page 74
... RHDX DATA IN t AVDV P2.0–P2.7 OR A8–A15 FROM DPF Figure 42. External Data Memory Read Cycle 74 Product data P83C654X2/P87C654X2 = Time for address valid to ALE LOW. =Time for ALE LOW to PSEN LOW. A0–A7 A8–A15 SU00006 A0–A7 FROM PCL INSTR IN A0–A15 FROM PCH ...
Page 75
... P2.0–P2.7 OR A8–A15 FROM DPF Figure 43. External Data Memory Write Cycle repeated START condition STOP condition SU;DAT1 HD;DAT 2 Figure 44. Timing I C interface 75 Product data P83C654X2/P87C654X2 A0–A7 FROM PCL INSTR IN A0–A15 FROM PCH SU00026 START condition t SU;STA 0.7 VDD 0.3 VDD t BUF ...
Page 76
... For timing purposes, a port is no longer floating when a 100mV change from max for a logic ‘0’. load voltage occurs, and begins to float when a 100mV change from the loaded level occurs SU00717 76 Product data P83C654X2/P87C654X2 SET TI VALID VALID VALID ...
Page 77
... Fri Apr 20 15:51:40 2001 equ 08Eh MOV AUXR,#001h ; turn off ALE LJMP LJMP_LABEL ; jump to end of address space NOP LJMP LJMP_LABEL NOP operational DD 77 Product data P83C654X2/P87C654X2 MAX ACTIVE MODE I MAX = 1.1 FREQ. + 1.0 CC TYP ACTIVE MODE MAX IDLE MODE I MAX = 0.22 FREQ. + 1.0 CC TYP IDLE MODE 36 SU01684 ...
Page 78
... CLCH CHCL RST P0 EA (NC) XTAL2 XTAL1 V SS SU00016 Test Condition, Power-down mode 5 Product data P83C654X2/P87C654X2 RST XTAL2 XTAL1 V SS SU00720 Test Condition, Idle Mode CC All other pins are disconnected SU00009 V ...
Page 79
... When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. Encryption Array 64 bytes of encryption array are initially unprogrammed (all 1s). 79 Product data P83C654X2/P87C654X2 source should be well regulated and free of glitches ...
Page 80
... Product data P83C654X2/P87C654X2 P2.6 P3.7 P3.6 P3 ...
Page 81
... GHGL t = 100 GLGH 1 Figure 56. PROG Waveform RST EA/V PP P3.6 ALE/PROG P3.7 OTP PSEN XTAL2 P2.7 P2.6 XTAL1 P2.0–P2 Figure 57. Program Verification 81 Product data P83C654X2/P87C654X2 +5V PGM DATA +12.75V 5 PULSES TO GROUND A8–A13 SU01746 SU00875 +5V PGM DATA ENABLE 0 A8–A13 SU01747 ...
Page 82
... OTP/ROM (See Figure 58) PARAMETER * ADDRESS DATA IN t GHDX t GHAX t GHGL t GHSL LOGIC 1 LOGIC 0 t ELQV Figure 58. EPROM Programming and Verification 82 Product data P83C654X2/P87C654X2 MIN MAX UNIT 12.5 13 MHz 48t CLCL 48t CLCL 48t CLCL 48t CLCL 48t ...
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... OTP/ROM, from the internal memory latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. Encryption Array 64 bytes of encryption array are initially unprogrammed (all 1s). 83 Product data P83C654X2/P87C654X2 ...
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... Apr OTP/ROM, BIT(S) 7:0 7 Disabled Disabled Yes If Yes, must send key file. 84 Product data P83C654X2/P87C654X2 COMMENT User ROM Data ROM Encryption Key FFH = no encryption ROM Security Bit enable security 1 = disable security ROM Security Bit enable security 1 = disable security ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 256B RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) PLCC44: plastic leaded chip carrier; 44 leads 2004 Apr OTP/ROM, 85 Product data P83C654X2/P87C654X2 SOT187-2 ...
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... Philips Semiconductors 80C51 8-bit microcontroller family 256B RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) LQFP44: plastic low profile quad flat package; 44 leads; body 1.4 mm 2004 Apr OTP/ROM, 86 Product data P83C654X2/P87C654X2 SOT389-1 ...
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... RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) REVISION HISTORY Rev Date Description _2 20040420 Product data (9397 750 13173) Modifications: Update Special Function Registers table. Remove P3.4 from Figures 55 and 57. _1 20030213 Product data (9397 750 10814) 2004 Apr OTP/ROM, 87 Product data P83C654X2/P87C654X2 ...
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... Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Fax: + 24825 Document order number: 88 Product data P83C654X2/P87C654X2 2 C patent Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 04-04 ...