STR91XFA STMICROELECTRONICS [STMicroelectronics], STR91XFA Datasheet
STR91XFA
Related parts for STR91XFA
STR91XFA Summary of contents
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... MHz ARM9E based MCU – ARM966E-S RISC core: Harvard archi- tecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash) – STR91xFA implementation of core adds high-speed burst Flash memory interface, instruction prefetch queue, branch cache – MIPS directly from Flash memory – ...
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... IRQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.9.3 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.10 Clock control unit (CCU 2.10.1 Master clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.10.2 Reference clock (RCLK 2.10.3 AHB clock (HCLK 2.10.4 APB clock (PCLK 2.10.5 Flash memory interface clock (FMICLK 2.10.6 Baud rate clock (BRCLK 2.10.7 External memory interface bus clock (BCLK 2.10.8 USB interface clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10.9 Ethernet MAC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/78 STR91xFA ...
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... STR91xFA 2.10.10 External RTC calibration clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10.11 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.11 Flexible power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.11.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.11.2 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.11.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.12 Voltage supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.12.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . . . . 18 2.12.2 Battery supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.13 System supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.13.1 Supply voltage brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.13.2 Supply voltage dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.13.3 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.13.4 External RESET_INn pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.13.5 Power- 2.13.6 JTAG debug command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 ...
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... Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.2.1 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . 49 6.3 LVD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.1 LVD delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.5 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.6 RESET_INn and power-on-reset characteristics . . . . . . . . . . . . . . . . . . . . . 54 6.7 Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.8 RTC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.9 PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.10 SRAM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4/78 STR91xFA ...
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... STR91xFA 6.11 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.12.1 Functional EMS (Electro Magnetic Susceptibility 6.12.2 Electro Magnetic Interference (EMI 6.12.3 Absolute Maximum Ratings (Electrical Sensitivity 6.12.4 Electro-Static Discharge (ESD 6.12.5 Static and Dynamic Latch- 6.12.6 Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . 58 6.12.7 Electrical Sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.13 External memory bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.14 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6 ...
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... For complete information on STR91xFA memory, registers, and peripherals, please refer to the STR91xFA Reference Manual. For information on programming the STR91xFA Flash memory please refer to the STR9 Flash Programming Reference Manual For information on the ARM966E-S core, please refer to the ARM966E-S Rev. 2 Technical Reference Manual ...
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... JTAG test/programming interface. 2.2 Package choice STR91xFA devices are available in 128-pin ( mm) 80-pin ( mm) LQFP and LFBGA144 ( mm) packages. Refer to the for a list of available peripherals for each of the package choices. 2.3 ...
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... Flash memory with the instructions that use them, but instead the literals are placed at some other address which looks like a program branch from the PFQ’s point of view. The STR91xFA implementation of the ARM966E-S core has special circuitry to prevent flushing the PFQ when literals are encountered in program flow to keep performance at a maximum ...
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... STR91xFA Figure 1. STR91xFA block diagram 1.8V GND 3.0 or 3.3V GND VBATT 4 MHz to 25 MHz XTAL EMI Ctrl USB Bus To Ethernet PHY (MII USB not available on STR910 ** Ethernet MAC not available on STR910 and STR911 *** EMI not available on LQFP80 **** Only 40 GPIOs on LQFP80 STR91xA Stacked Burst Flash Memory Die ...
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... Section 2.5.1. Efficient DMA transfers are managed by firmware using linked list descriptor tables. Of the 16 DMA request signals, two are assigned to external inputs. The DMA unit can move data between external devices and resources inside the STR91xFA through the EMI bus. 2.7 Non-volatile memories There are two independent 32-bit wide Burst Flash memories enabling true read-while-write operation ...
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... Product ID and revision level OTP bytes 31 and 30 are programmed at ST factory before shipment and may be read by firmware to determine the STR91xFA product type and silicon revision so it can optionally take action based on the silicon on which it is running. Byte 31 contains the the major family identifier of " ...
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... The STR91xFA has a feature to reduce ISR response time for IRQ interrupts. Typically, it requires two memory accesses to read the interrupt vector address from the VIC, but the STR91xFA reduces this to a single access by adding a 16th entry in the instruction branch cache, dedicated for interrupts. This 16th cache entry always holds the instruction that reads the interrupt vector address from the VIC, eliminating one of the memory accesses typically required in traditional ARM implementations ...
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... The 32 interrupt request signals coming into the VIC on 32 IRQ channels are from various sources; 5 from a wake-up unit and the remaining 27 come from internal sources on the STR91xFA such as on-chip peripherals, see interrupt on any IRQ channel. One of the 5 interrupt requests generated by the wake-up unit (IRQ25 in from the logical OR of all 32 inputs to the wake-up unit ...
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... CPU can switch between the three CCU inputs without introducing any glitches on the master clock output. Inputs to the CCU are: ● Main Oscillator (f crystal connected to STR91xFA pins X1_CPU and X2_CPU external oscillator device connected to pin X1_CPU. ● PLL (f ) ...
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... STR91xFA As an option, there are a number of peripherals that do not have to receive a clock sourced from the CCU. The USB interface can receive an external clock on pin P2.7, TIM timers TIM0/ TIM1 can receive an external clock on pin P2.4, and timers TIM2/TIM3 on pin P2.5. Figure 2. Clock control 32.768 kHz ...
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... A 25 MHz clock signal coming from a dedicated output pin (P5.2) of the STR91xFA. In this case, the STR91xFA must use a 25 MHz signal on its main oscillator input in order to pass this 25 MHz clock back out to the PHY device through pin P5.2. The advantage here is that an inexpensive 25 MHz crystal may be used to source a clock to both the STR91xFA and the external PHY device ...
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... PLL as needed. 2.11 Flexible power management The STR91xFA offers configurable and flexible power management control that allows the user to choose the best power option to fit the application. Power consumption can be dynamically managed by firmware and hardware to match the system’s requirements. Power management is provided via clock control to the CPU and individual peripherals ...
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... ADC supply isolation. On 80-pin packages, the analog voltage supply is shared with the ADC reference voltage pin (as described next), and the analog ground is shared with the digital ground at a single point in the STR91xFA device on pin AVSS_VSSQ. ...
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... Firmware may also disable the LVD completely for lowest-power operation when an external LVD device is being used. 2.13.3 Watchdog timer The STR91xFA has a 16-bit down-counter (not one of the four TIM timers) that can be used as a watchdog timer general purpose free-running timer/counter. The clock source is the ) drop out or brown out ...
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... RESET_INn pin. A valid active-low input signal of t reset within the STR91xFA. There is also a RESET_OUTn pin on the STR91xFA that can drive other system components on the circuit board. RESET_OUTn is active-low and has the same timing of the Power-On-Reset (POR) shown next ...
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... JTRSTn are all standard JTAG signals complying with the IEEE-1149.1 specification. The sixth signal, JRTCK (Return TCK output from the STR91xFA and it is used to pace the JTCK clock signal coming in from the external JTAG test equipment for debugging. The frequency of ...
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... JTDI JRTCK 2.15.1 In-system-programming The JTAG interface is used to program or erase all memory areas of the STR91xFA device. The pin RESET_INn must be asserted during ISP to prevent the CPU from fetching invalid instructions while the Flash memories are being programmed. Note that the 32 bytes of OTP memory locations cannot be erased by any means once programmed by JTAG ISP or the CPU ...
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... Embedded trace module (ARM ETM9, v. r2p2) The ETM9 interface provides greater visibility of instruction and data flow happening inside the CPU core by streaming compressed data at a very high rate from the STR91xFA though a small number of ETM9 pins to an external Trace Port Analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or other high-speed channel ...
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... Medium Independent Interface (MII). The STR91xFA requires an external Ethernet physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the STR91xFA MII port using as many as 18 signals (see pins which have signal names MII_* in The MAC corresponds to the OSI Data Link layer and the PHY corresponds to the OSI Physical layer. The STR91xFA MAC is responsible for: ● ...
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... USB pins. 2.19 CAN 2.0B interface The STR91xFA provides a CAN interface complying with CAN protocol version 2.0 parts A and B. An external CAN transceiver device connected to pins CAN_RX and CAN_TX is required for connection to the physical CAN bus. The CAN interface manages Message Objects and Identifier Masks using a Message SRAM and a Message Handler ...
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... The CAN interface is not supported by DMA. 2.20 UART interfaces with DMA The STR91xFA supports three independent UART serial interfaces, designated UART0, UART1, and UART2. Each interface is very similar to the industry-standard 16C550 UART device. All three UART channels support IrDA encoding/decoding, requiring only an external LED transceiver to pins UARTx_RX and UARTx_Tx for communication ...
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... I C interfaces with DMA The STR91xFA supports two independent I2C serial interfaces, designated I2C0, and I2C1. Each interface allows direct connection to an I2C bus as either a bus master or bus slave device (firmware configurable). I2C is a two-wire communication channel, having a bi- directional data signal and a single-directional clock signal based on open-drain line drivers, requiring external pull-up resistors ...
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... Functional overview high-impedance state when not selected. The STR91xFA supports SPI multi-Master operation because it provides collision detection. Each SSP interface on the STR91xFA has the following features: ● Full-duplex, three or four-wire synchronous transfers ● Master or Slave operation ● Programmable clock bit rate with prescaler MHz for Master mode and 4 MHz for Slave mode ● ...
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... DMA single-transfer. 2.25 Standard timers (TIM) with DMA The STR91xFA has four independent, free-running 16-bit timer/counter modules designated TIM0, TIM1, TIM2, and TIM3. Each general purpose timer/counter can be configured by firmware for a variety of tasks including; pulse width and frequency measurement (input capture), generation of waveforms (output compare and PWM), event counting, delay timing, and up/down counting ...
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... External memory interface (EMI) STR91xFA devices in 128-pin and 144-ball packages offer an external memory bus for connecting external parallel peripherals and memories. The EMI bus resides on ports 7, 8, and 9 and operates with either 16-bit data path. The configuration bit mode is specified by CPU firmware writing to configuration registers at run-time ...
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... STR91xFA The EMI has the following features: ● Supports static asynchronous memory access cycles, including page mode for non-mux operation. The bus control signals include: – EMI_RDn - read signal x16 mode – EMI_BWR_WRLn - write signal in x8 mode and write low byte signal in x16 mode – ...
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... ST R91xx EMI_CS3n EMI_CS2n EMI_CS1n EMI_CS0n EMI_BWR_WRLn EMI_RDn EMI_ALE P8.7 EMI_AD7 P8.6 EMI_AD6 P8.5 EMI_AD5 P8.4 EMI_AD4 P8.3 EMI_AD3 P8.2 EMI_AD2 P8.1 EMI_AD1 P8.0 EMI_AD0 STR91xFA 16-BIT DEVICE CHIP_SELECT WRITE_HIGH_BYTE WRITE_LOW_BYTE READ ADDR_LATCH A23 A22 A21 A20 A19 A18 A17 A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 ...
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... STR91xFA Figure 6. EMI 8-bit non-multiplexed connection example STR91xx EMI_BWR_WRLn EMI_CS3n EMI_CS2n EMI_CS1n EMI_CS0n EMI_RDn P9.7 EMI_A15 P9.6 EMI_A14 P9.5 EMI_A13 P9.4 EMI_A12 P9.3 EMI_A11 P9.2 EMI_A10 P9.1 EMI_A9 P9.0 EMI_A8 P7.7 EMI_A7 P7.6 EMI_A6 P7.5 EMI_A5 P7.4 EMI_A4 P7.3 EMI_A3 P7.2 EMI_A2 P7.1 EMI_A1 P7.0 EMI_A0 P8.7 EMI_D7 P8.6 EMI_D6 P8.5 EMI_D5 P8.4 EMI_D4 P8.3 EMI_D3 P8.2 EMI_D2 P8.1 EMI_D1 P8.0 EMI_D0 Functional overview 8-BIT ...
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... Related documentation 3 Related documentation Available from www.arm.com: ARM966E-S Rev 2 Technical Reference Manual Available from www.st.com: STR91xFA Reference Manual STR9 Flash Programming Manual (PM0020) The above is a selected list only, a full list STR91xFA application notes can be viewed at http://www.st.com. 34/78 STR91xFA ...
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... STR91xFA 4 Pin description Figure 7. STR91xFAM 80-pin package pinout P4.3 P4.2 P4.1 P4.0 VSS_VSSQ VDDQ P2.0 P2.1 P5.0 VSS VDD P5.1 P6.2 P6.3 VDDQ VSSQ P5.2 P5.3 P6.0 P6 (Not Used) on STR910FAM devices. Pin 59 is not connected, pin 60 must be pulled 1.5Kohm resistor to VDDQ USBCLK function on STR910FAM devices STR91xFAM 10 11 ...
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... Pin description Figure 8. STR91xFAW 128-pin package pinout P4.2 P4.1 P4.0 AVSS P7.0 P7.1 P7.2 VSSQ VDDQ P2.0 P2.1 P5.0 P7.3 P7.4 P7.5 VSS VDD P5.1 P6.2 P6.3 EMI_BWR_WRLn EMI_WRHn VDDQ VSSQ (3) PHYCLK_P5.2 P8.0 P5.3 P8.1 P6.0 P8.2 P6.1 P8 (Not Used) on STR910FAW devices. Pin 95 is not connected, pin 96 must be pulled 1.5Kohm resistor to VDDQ USBCLK function on STR910FAW devices PHYCLK function on STR910FAW devices. ...
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... STR91xFA 4.1 LFBGA144 ball connections ● In Table 4. balls labelled NC are no connect balls. These NC balls are reserved for future devices and should NOT be connected to ground or any other signal. There are total (no connection) balls. ● Balls H1 and G4 are assigned as EMI bus write signals (EMI_BWR_WRLn and EMI_WRHn) ...
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... PHY Rx data0 GP Output MII_RXD1, I2C1_DIN, GPIO_0.3, PHY Rx data I2C data in GP Output MII_RXD2, TIM0_ICAP1, GPIO_0.4, PHY Rx data Input Capture GP Output STR91xFA Table 5. using a 100 K Ω resistor, all unused Alternate functions Alternate Alternate Output 2 Output 3 I2C0_CLKOUT, I2C ETM_PCK0, ETM clock out Packet I2C0_DOUT, ...
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... STR91xFA Pkg Default Pin Pin Name Function GPIO_0. F11 P0.5 I/O GP Input, HiZ GPIO_0. E11 P0.6 I/O GP Input, HiZ GPIO_0. B12 P0.7 I/O GP Input, HiZ GPIO_1. B10 P1.0 I/O GP Input, HiZ GPIO_1. C10 P1.1 I/O GP Input, HiZ GPIO_1.2, - 101 B9 P1.2 I/O GP Input, HiZ GPIO_1.3, - 106 C8 P1.3 I/O GP Input, HiZ GPIO_1.4, - 109 B7 P1.4 I/O GP Input, HiZ GPIO_1 ...
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... Input Capture GP Output EXINT20, TIM2_ICAP1, GPIO_6.4, External Intr Input Capture GP Output EXINT21, TIM2_ICAP2, GPIO_6.5, External Intr Input Capture GP Output STR91xFA Alternate functions Alternate Alternate Output 2 Output 3 SSP1_MOSI, CAN_TX, SSP mstr dat out CAN Tx data SSP1_NSS, TIM1_OCMP1, Out comp/PWM SSP mstr sel out ...
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... STR91xFA Pkg Default Pin Pin Name Function GPIO_6. P6.6 I/O GP Input, HiZ GPIO_6. D12 P6.7 I/O GP Input, HiZ GPIO_7. P7.0 I/O GP Input, HiZ GPIO_7. P7.1 I/O GP Input, HiZ GPIO_7. P7.2 I/O GP Input, HiZ GPIO_7. P7.3 I/O GP Input, HiZ GPIO_7. P7.4 I/O GP Input, HiZ GPIO_7. P7.5 I/O GP Input, HiZ GPIO_7 ...
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... RTC crystal X2_RTC O connection JTAG return 61 97 B11 JRTCK O clock or RTC clock JTAG TAP 67 107 D8 JTRSTn I controller reset 68 108 E8 JTCK I JTAG clock 42/78 Default Input Alternate Alternate Function Input 1 Output 1 GPIO_9. Output STR91xFA Alternate functions Alternate Alternate Output 2 Output 3 8b) EMI_A15, - 16b)EMI_AD15 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ...
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... STR91xFA Pkg Default Pin Pin Name Function JTAG mode 69 111 A6 JTMS I select 72 115 C6 JTDI I JTAG data in 73 117 B6 JTDO O JTAG data out ADC analog - 122 A3 AVDD V voltage source, 2.7V - 3.6V ADC analog - 4 C3 AVSS G ground Common ground AVSS point for digital I/ _VSSQ O & ...
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... SRAM appears in the buffered AHB range. Beginning at CPU address 0x5000.0000, SRAM is in non-buffered AHB range. The SRAM size must be specified by CPU intitialization firmware writing to a control register after any reset condition. Default SRAM size is 32K bytes, with option to set to 64K bytes on STR91xFAx3x devices, and to 96K bytes on STR91xFAx4x devices. 44/78 ...
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... Optional configuration Using the STR91xFA device configuration software tool, or IDE from 3rd party, one can specify that the smaller secondary Flash memory is at the boot location at reset and the primary Flash is disabled. The selection of which Flash memory is at the boot location is programmed in a non-volatile Flash-based configuration bit during JTAG ISP ...
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... Memory mapping Notes for Figure 9: STR91xFA memory map on page Notes: 1 Either of the two Flash memories may be placed at CPU boot address 0x0000.0000. By default, the primary Flash memory is in boot position starting at CPU address 0x0000.0000 and the secondary Flash memory may be placed at a higher address following the end of the primary Flash memory ...
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... STR91xFA Figure 9. STR91xFA memory map TOTAL 4 GB CPU MEMORY SPACE 0xFFFF.FFFF VIC0 0xFFFF.F000 RESERVED 0xFC01.0000 VIC1 0xFC00.0000 RESERVED 0x8000.0000 ENET 0x7C00.0000 8-CH DMA 0x7800.0000 EMI 0x7400.0000 USB 0x7000.0000 ENET 0x6C00.0000 8-CH DMA 0x6800.0000 EMI 0x6400.0000 USB 0x6000.0000 APB1 0x5C00.0000 APB0 0x5800.0000 FMI 0x5400.0000 ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (V voltage on pins with respect to ground (V 48/78 Parameter (80-pin package must not exceed the recommended values. SSQ STR91xFA Value Unit Min Max -0.3 2.4 SS -0.3 4.0 SS -0.3 4 ...
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... STR91xFA 6.2 Operating conditions Table 7. Operating conditions Symbol V Digital CPU supply voltage DD V Digital I/O supply voltage DDQ SRAM backup and RTC supply (1) V BATT voltage Analog ADC supply voltage AV DD (128-pin and 144-ball packages) Analog ADC reference voltage AV REF (128-pin and 144-ball packages) ...
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... Test Parameter Conditions rise DD fall DD rise (1)(2) DDQ fall (1)(2) DDQ (1)(2) rise (2)(3) DDQ fall (2)(3) DDQ (2)(3) reaches the V threshold after the first ~10 ms delay (introduced DDQ_LVD+ ~10 ms delay reaches the V threshold before the first ~10 ms delay DDQ_LVD+ STR91xFA Value Min Typ Max 1.43 1.50 1.58 1.33 1.40 1.47 1.65 2.32 2.45 2.57 2.23 2.35 2.46 2.65 2.61 2.75 2.89 2.52 2.65 2.78 2.95 V DDQ_LVD+ ~10 ms delay Figure 11 ...
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... STR91xFA Figure 11. LVD reset delay case (green (red) DDQ RESET_OUTn (blue) 6.4 DC electrical characteristics V = 2.7 - 3.6V, V DDQ Table 10. DC Electrical Characteristics Symbol Parameter V Input High Level IH V Input Low Level IL Input Hysteresis V HYS Schmitt Trigger Output High Level High current pins ...
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... All peripherals off All peripherals on All peripherals off (5) LVD On (5) LVD Off (4) LVD On (4) LVD Off Measured on VBATT pin Value Min Typ 1.7 CPU_CLK = 96 MHz (1)(2)(5) 1.3 (2)(3)(5) 1.14 (2)(4)(5) 0. 0.3 5 STR91xFA Unit Max 2.3 mA/ MHz 1.6 mA/ 1.7 MHz mA/ 0.75 MHz 825 µA 820 µA TBD µA TBD µA 0.9 µA 85 µA ...
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... STR91xFA Figure 12. Sleep Mode current vs temperature with LVD on 2000 1800 1600 1400 1200 1000 800 600 400 200 -40 -20 Table 12. AC electrical characteristics Symbol Parameter f CCU Master Clk Output MSTR f CPU Core Frequency CPUCLK f Peripheral Clock for APB PCLK f Peripheral Clock for AHB ...
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... DD A Test Conditions Stable V DDQ = 1. °C unless otherwise specified Test Conditions (1) (1) Stable V DDQ Value (1) Typ Max Min 100 10 one PCLK Value Min Typ Max ( Value Min Typ Max (2)1) LVD 1 DDQ STR91xFA Unit Unit mS Unit V S ...
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... STR91xFA Table 16. RTC crystal electrical characteristics Symbol Parameter f Resonant frequency O R Series resistance S C Load capacitance L 6.9 PLL electrical characteristics V = 2.7 - 3.6V, V DDQ Table 17. PLL Electrical Characteristics Symbol Parameter f PLL Output Clock PLL f Clock Input OSC t PLL lock time LOCK ∆ PLL Jitter (peak to peak) ...
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... Secondary Bank (32 Kbytes) Of Primary Bank (64 Kbytes) Sector program Of Secondary Bank (8 Kbytes) Word program Notes: 1 STR91xFAxx4 devices have 512 Kbytes primary Flash, STR91xFAxx2 devices have 256 Kbytes primary Flash 1.8V 3.3V DD DDQ 3 Flash read access for synchronous addresses is 96 MHz maximum. 4 Flash read access for asynchronous accesses requires 2 wait states when FMI clock is above 66 MHz ...
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... STR91xFA 6.12 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 6.12.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ● ...
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... Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: ● Corrupted program counter ● Unexpected reset 58/78 Ratings Conditions =+25° STR91xFA Maximum Unit 1) value +/-2000 V 1000 ...
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... STR91xFA ● Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values ...
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... EMI_CSxn EMI_A LE EMI_A [23:16] EMI_A D[15:0] EMI_RDn 60/78 Value Min BCLK BCLK BCLK A ddress tRA ddress ddress tRA S STR91xFA Unit Max BCLK WSTRD can be programmed tRCR tRA H Data tRDS tRDH tRP tRCR tRA H Data tRDS tRDH tRP ...
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... STR91xFA Table 26. EMI write operation Symbol Parameter t WRn to CSn inactive WCR t Write Pulse Width WP Write Data Setup Time (non-mux mode) t WDS Write Data Setup Time (mux mode ) Write Data Hold t WDH Time Write Address Setup t WAS Time Write Address Hold t WAH ...
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... Figure 15. Non-Mux Bus (8-bit) write timings EMI_CSxn EMI_A[15:0] EMI_D[7:0] EMI_BWR_WRLn Figure 16. Mux Bus (16-bit) Write Timings EMI_CSxn EMI_A LE EMI_A [23:16] EMI_A D[15:0] EMI_WRLn EMI_WRHn 62/78 Address Data tWAS tWDS ddress tWDS A ddress tWA S STR91xFA tWCR tWAH tWP tWDH tWCR tWA H Data tWDH tWP ...
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... STR91xFA 6.14 ADC electrical characteristics V = 2.7 - 3.6V, V DDQ Table 27. ADC electrical characteristics Symbol Parameter V Input Voltage Range AIN RES Resolution N Number of Input Channels CH f ADC Clock Frequency ADC t POR bit set to Standby mode POR(ADC) (1) t Conversion Time CONV TR Throughput Rate C Input Capacitance IN E Differential Non-Linearity ...
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... IDEAL 6 7 1021 1022 1023 1024 AV STR91xFA (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line E =Total Unadjusted Error: maximum T deviation between the actual and the ide- al transfer curves. E =Offset Error: deviation between the ...
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... STR91xFA 6.15 Communication interface electrical characteristics 6.15.1 10/100 Ethernet MAC electrical characteristics V = 2.7 - 3.6V, V DDQ Ethernet MII Interface Timings Figure 18. MII_RX_CLK and MII_TX_CLK timing diagram MII_RX_TCLK, MII_TX_CLK Table 28. MII_RX_CLK and MII_TX_CLK timing table Symbol 1 Cycle time 2 Pulse duration HIGH 3 Pulse duration LOW 4 Transition time Figure 19 ...
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... T (MDIO (MDIO Parameter Symbol t (MII_TX_EN) VAL T (MII_TX_EN) inval T (MII_CRS (MII_CRS (MII_COL (MII_COL (MII_TXD) VAL T (MII_TXD inval STR91xFA Value Unit Min Max 2.83 ns 2.70 ns -2. Value Unit Min Max 4.20 ns 4.86 ns 0.61 ns 0.00 ns 0.81 ns 0.00 ns 5.02 ns 5.02 ns ...
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... STR91xFA Ethernet MII Receive timings Figure 22. Ethernet MII receive timing diagram MII_RX_CLK MII_RXD MII_RX_DV MII_RX_ER Figure 23. Ethernet MII receive timing table Symbol MII_RXD valid to 1 MII_RX_CLK high MII_RX_CLK high to 2 MII_RXD invalid 6.15.2 USB electrical interface characteristics USB 2.0 Compliant in Full Speed Mode 6 ...
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... The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal total capacitance of one bus line 68/78 = 1. °C unless otherwise specified Standard I Parameter Min 4.7 4.0 4.7 4.0 4.7 0 250 4.0 STR91xFA Fast I C Max Min Max 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1C 1000 300 b 20+0.1C ...
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... STR91xFA 6.15.5 SPI electrical characteristics V = 2.7 - 3.6V, V DDQ Table 33. SPI electrical characteristics Symbol f SCLK SPI clock frequency 1/t c(SCLK) t r(SCLK) SPI clock rise and fall times t f(SCLK setup time su(SS hold time h(SS) t w(SCLKH) SCLK high and low time t w(SCLKL) t su(MI) Data input setup time ...
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... MOSI OUTPUT 70/78 t c(SCLK) t w(SCLKH w(SCLKL) v(SO) MSB OUT BIT6 OUT su(SI) h(SI) MSB IN t c(SCLK) t w(SCLKH) t w(SCLKL h(MI) su(MI) MSB v(MO) h(MO) MSB OUT BIT6 OUT t h( NSS ) t h(SO) t r(SCLK) t f(SCLK) LSB OUT BIT1 IN LSB IN t r(SCLK) t f(SCLK) BIT6 IN LSB IN LSB OUT STR91xFA t dis(SO) ...
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... STR91xFA 7 Package mechanical data Figure 27. 80-Pin Low Profile Quad Flat Package SEATING PLANE C ccc PIN 1 IDENTIFICATION 0.25 mm GAGE PLANE Package mechanical data mm inches Dim. Min Typ Max Min Typ A 1.60 A1 0.05 0.15 0.0020 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0 ...
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... PLANE C ccc 128 1 e PIN 1 IDENTIFICATION 72/78 0.25 mm GAGE PLANE STR91xFA mm inches Dim. Min Typ Max Min Typ A 1.60 A1 0.05 0.15 0.0020 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.13 0.18 0.23 0.0051 0.0071 0.0091 c 0.09 0.20 0.0035 D 15.80 16.00 16.20 0.6220 0.6299 0.6378 D1 13.80 14.00 14.20 0.5433 0.5512 0.5591 D3 12.40 0.4882 E 15.80 16.00 16.20 0.6220 0.6299 0.6378 E1 13 ...
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... STR91xFA Figure 29. 144-Low Profile Fine Pitch Ball Grid Array Package Figure 30. Recommended PCB Design rules (0.80/0.75mm pitch BGA) Dpad Dsm Solder paste – Non solder mask defined pads are recommended – mils screen print Dpad Dsm Package mechanical data mm inches Dim ...
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... JA and INT I/O D INT and V , expressed in Watts. This is the Chip Internal DD DD < P and may be neglected. On the other hand, I/O INT of the STR91xFA is 500mW (I INT and (at equilibrium) for a known T D Parameter STR91xFA ), I 250mA x 2.0V). ...
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... STR91xFA 8 Ordering information Table 35. Ordering information Part Number STR910FAM32X6 STR910FAW32X6 STR910FAZ32H6 STR911FAM42X6 STR911FAM44X6 STR911FAW42X6 STR911FAW44X6 STR912FAW34X6 STR912FAW42X6 STR912FAW44X6 STR912FAZ42H6 STR912FAZ44H6 Flash KB RAM KB Major Peripherals 256+32 64 256+32 64 CAN, EMI, 80 I/Os 256+32 64 CAN, EMI, 80 I/Os 256+32 96 USB, CAN, 40 I/Os 512+32 96 256+32 96 USB, CAN, EMI, 80 I/Os 512+32 96 512+32 ...
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... Package X = plastic LQFP H = LFBGA Temperature Range 6 = -40 to 85°C Shipping Option T = Tape & Reel Packing For a list of available options (e.g. speed, package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 76/78 STR9 STR91xFA ...
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... STR91xFA 9 Revision history Table 37. Revision history Date Revision 09-May-2007 1 Initial release Revision history Changes 77/78 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 78/78 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STR91xFA ...