R5F21133DFP RENESAS [Renesas Technology Corp], R5F21133DFP Datasheet - Page 179

• Manufacturer Part Number: R5F21133DFP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

R8C/13 Group
Rev.1.20
REJ09B0111-0120
Operation mode
Areas in which a
rewrite control
program can be located
Areas in which a
rewrite control
program can be executed before being executed
Areas which can be
rewritten
Software command
limitations
Modes after Program or
Erase
CPU status during Auto
Write and Auto Erase
Flash memory status
detection
Conditions for
transferring to
erase-suspend
CPU Clock
NOTES:
17.4 CPU Rewrite Mode
1. When setting the FMR02 bit in the FMR0 register to “1” (rewrite enabled) and the FMR15 bit in the FMR1
Table 17.3 EW0 Mode and EW1 Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the
CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-
board without having to use a ROM programmer, etc. Make sure the Program and the Block Erase
commands are executed only on each block in the user ROM area.
For interrupts requested during an erase operation in CPU rewrite mode, the R8C/11 flash module offers
an "erase-suspend" feature which allow the erase operation to be suspended, and access made avail-
able to the flash.
During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or
Erase Write 1 (EW1) mode. Table 17.3 lists the differences between Erase Write 0 (EW0) and Erase
Write 1 (EW1) modes.
register to “0” (rewrite enabled), the Block 0 is rewritable. When setting the FMR16 bit to “0” (rewrite
enabled), the Block 1 is rewritable.
Jan 27, 2006
Item
page 168 of 205
Single chip mode
User ROM area
Must be transferred to any area other Can be executed directly in the user
than the flash memory (e.g., RAM)
User ROM area
None
Read Status Register mode
Operating
• Read the FMR0 register FMR00,
• Execute the Read Status Register
Set the FMR40 and FMR41 bits in
the FMR4 register to “1” by program. enabled occurs while the FMR40 bit in
5MHz or below
FMR06, and FMR07 bits in a
program
command to read the status
register SR7, SR5, and SR4.
EW0 mode
Single chip mode
User ROM area
ROM area
User ROM area
• Program, Block Erase command
• Read Status Register command
Read Array mode
Hold state (I/O ports retain the state in
which they were before the command
was executed)
Read the FMR0 register FMR00,
FMR06, and FMR07 bits in a program
When an interrupt which is set for
the FMR4 register is set to “1”.
No restriction to the following
(clock frequency to be used)
block in which a rewrite control program
However, this does not include the
exists
Cannot be executed on any block in
which a rewrite control program exists
Cannot be executed
(1)
EW1 mode
17.4 CPU Rewrite Mode