78Q2123CGV/F TERIDIAN [Teridian Semiconductor Corporation], 78Q2123CGV/F Datasheet
78Q2123CGV/F
Related parts for 78Q2123CGV/F
78Q2123CGV/F Summary of contents
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DESCRIPTION The 78Q2123 and 78Q2133, MicroPHY smallest 10BASE-T/100BASE-TX transceivers in the market. They include integrated MII, ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions. The transmitter includes an on-chip pulse- shaper and a low-power line driver. The receiver has ...
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FUNCTIONAL DESCRIPTION GENERAL Power Management The 78Q2123 and 78Q2133 have three power saving modes: • Chip Power-Down • Receive Power Management • Transmit High Impedance Mode Chip power-down is activated by setting the PWRDN bit in MII register MR0.11. When ...
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In 10BASE-T mode, the 20MHz receive clock is recovered digitally from the Manchester data using a DLL locked to the reference clock. Manchester-coded preambles are detected, the CDR immediately re-aligns the phase of the clock to synchronize with the incoming ...
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Polarity Correction The 78Q2123/78Q2133 are capable of either automatic or manual polarity reversal for 10BASE-T and auto- negotiation functions. Register bits MR16.5 and MR16.4 control this feature. The default is automatic mode where MR16.5 is low and MR16.4 indicates if ...
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MEDIA INDEPENDENT INTERFACE MII Transmit and Receive Operation The MII interface on the 78Q2123/78Q2133 provide independent transmit and receive paths for both 10Mb/s and 100Mb/s data rates as described in Clause 22 of the IEEE-802.3 standard. The transmit clock, TX_CLK, ...
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Automatic MDI/ MDI-X Configuration The 78Q2123/78Q2133 implement the automatic MDI/MDI-X configuration detailed in IEEE-802.3 2002. This function eliminates the need for cross over cables when connecting to another device. When auto-switching is 78Q2123/78Q2133 will attempt to detect activity on its ...
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PIN DESCRIPTION LEGEND TYPE DESCRIPTION A Analog Pin CIU TTL-level Input w/ Pull-up CIS TTL-level Input w/ Schmitt Trigger CO CMOS Output S Supply MII (MEDIA INDEPENDENT INTERFACE) SIGNAL PIN TYPE DESCRIPTION TX_CLK 15 COZ TRANSMIT CLOCK: TX_CLK is a ...
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MII (MEDIA INDEPENDENT INTERFACE) (CONTINUED) SIGNAL PIN TYPE DESCRIPTION RX_DV 11 COZ RECEIVE DATA VALID: RX_DV is asserted high to indicate that valid data is present on the RXD[3:0] pins. In 100BASE-TX mode, it transitions high with the first nibble ...
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MDI (MEDIA DEPENDENT INTERFACE) SIGNAL PIN TYPE DESCRIPTION TXOP, 30,31 A TRANSMIT OUTPUT POSITIVE/NEGATIVE: Transmitter differential outputs for TXON both 10base-T and 100base-TX. RXIP, 28,27 A RECEIVE INPUT POSITIVE/NEGATIVE: Receiver differential inputs for both RXIN 10BASE-T and 100BASE-TX. OSCILLATOR/CLOCK SIGNAL ...
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LED SIGNALS (PROGRAMMABILITY IS SECONDARY REQUIREMENT) SIGNAL PIN TYPE DESCRIPTION 4 CO PROGRAMMABLE LED. Active low. Default status: LINK OK. Active to indicate LED0 link with far end PHY PROGRAMMABLE LED. Active low. Default status ...
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REGISTER DESCRIPTION The 78Q2123/78Q2133 implement 13 16-bit registers, which are accessible via the MDIO and MDC pins. The supported registers are shown below in the following table. Attempts to read unsupported registers will be ignored and the MDIO pin will ...
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MR0: Control Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 0.15 RESET R/WC 0.14 LOOPBK R/W 0.13 SPEEDSL R/W 0.12 ANEGEN R/W 0.11 PWRDN R/W 0.10 ISO R/W 0.9 RANEG R/WC 0.8 DUPLEX R/W 0.7 COLT R/W 0.6:0 RSVD R Page: 12 ...
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MR1: Status Register Bits 1.15 through 1.11 reflect the ability of the 78Q2123/78Q2133. They do not reflect any ability changes made via the MII Management interface to bits 0.13 (SPEEDSL) , 0.12 (ANEGEN) and 0.8 (DUPLEX) in the Control Register. ...
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MR1: Status Register (continued) BIT SYMBOL TYPE DEFAULT DESCRIPTION 1.4 RFAULT RC 1.3 ANEGA R 1.2 LINK R 1.1 JAB RC 1.0 EXTD R MR2: PHY Identifier Register 1 BIT SYMBOL TYPE VALUE 2.15:0 OUI R 000Eh [23:6] MR3: PHY ...
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MR4: Auto-Negotiation Advertisement Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 4. 4.14 RSVD R 4.13 RF R/W 4. 4.11 A6 R 4.8 A3 R/W 4.7 A2 R/W 4.6 A1 R/W 4.5 ...
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MR5: Auto-Negotiation Link Partner Ability Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 5. 5.14 ACK R 5. 5.12:5 A7:0 R 5.4:0 S4:0 R MR6: Auto-Negotiation Expansion Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 6.15:5 RSVD R 6.4 PDF ...
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MR16: Vendor Specific Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 16.15 RPTR R/W 16.14 INPOL R/W 16.13 RSVD R 16.12 TXHIM R/W 16.11 SQEI R/W 16.10 NL10 R/W 16.9 RSVD R 16.8 RSVD R 16.7 RSVD R 16.6 RSVD R 16.5 ...
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MR16: Vendor Specific Register (continued) BIT SYMBOL TYPE DEFAULT DESCRIPTION 16.1 PCSBP R/W 16.0 RXCC R/W MR17: Interrupt Control/Status Register The Interrupt Control/Status Register provides the means for controlling and observing the events, which trigger an interrupt on the INTR ...
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MR17: Interrupt Control/Status Register (continued) BIT SYMBOL TYPE DEFAULT DESCRIPTION 17.3 LP-ACK_INT RC 17.2 LS-CHG_INT RC 17.1 RFAULT_INT RC 17.0 ANEG- RC COMP_INT MR18: Diagnostic Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 18.15:13 RSVD R 18.12 ANEGF RC 18.11 DPLX R ...
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MR19: Transceiver Control BIT SYMBOL TYPE DEFAULT DESCRIPTION 19.15:14 TXO[1:0] R/W 19.13:0 RSVD R MR20: Reserved BIT SYMBOL TYPE DEFAULT DESCRIPTION 20.15:0 Reserved NA MR21: Reserved BIT SYMBOL TYPE DEFAULT DESCRIPTION 21.15:0 Reserved NA MR22: Reserved BIT SYMBOL TYPE DEFAULT ...
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MR23: LED Configuration Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 23.15:8 Reserved NA 23.7:4 LED1[3:0] R/W 23.3:0 LED0[3:0] R/W Page <0000> Must set to zero on each write to MR23 <1h> 0000 = Link OK 0001 = RX ...
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MR24: MDI/MDIX Control Register BIT SYMBOL TYPE DEFAULT DESCRIPTION 24.15:8 Reserved R 24.7 PD_MODE R/W 24.6 AUTO_SW R/W 24.5 MDIX R/W 24.4 MDIX_CM R 24.3:0 MDIX_SD R/W Page Reserved 1 Write a ‘1’ to this bit ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation above maximum rating may permanently damage the device. PARAMETER DC Supply Voltage (Vcc) Storage Temperature Pin Voltage (except TXOP/N) Pin Voltage (TXOP/N only) Pin Current RECOMMENDED OPERATING CONDITIONS Unless otherwise noted, all specifications are ...
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DIGITAL I/O CHARACTERISTICS: Pins of type CI, CIU, CID, CIO: PARAMETER Input Voltage Low Input Voltage High Input Current Pull-up Resistance Input Capacitance Pins of type CIS: PARAMETER Low-to-High Threshold High-to-Low Threshold Input Current Input Capacitance Input Hystersis Pins of ...
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Pins of type CIO: PARAMETER Output Voltage Low Output Voltage High Output Transition Time DIGITAL TIMING CHARACTERISTICS RST Characteristics VCC Oscillator RST PARAMETER RST Pulse Assertion Page SYMBOL CONDITIONS Vol Iol = 4mA Voh Ioh = -4mA ...
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MII Transmit Interface CHARACTERISTICS Setup Time: TX_CLK to TXD[3:0], TX_EN, TX_ER Hold Time: TX_CLK to TXD[3:0], TX_EN, TX_ER CKIN-to-TX_CLK Delay TX_CLK Duty-Cycle MII Receive Interface CHARACTERISTICS Receive Output Delay: RX_CLK to RXD[3:0], RX_DV, RX_ER RX_CLK Duty-Cycle RX_CLK RXD[3:0] RX_DV or ...
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MDIO Interface Input Timing CHARACTERISTICS Setup Time: MDC to MDIO Hold Time: MDC to MDIO Max Frequency: MDC MDIO Interface Output Timing CHARACTERISTICS MDC to MDIO data delay MDIO output from high Z to driven after MDC MDIO output from ...
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MDIO Interface Output Timing Page © 2009 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver Rev 1.5 ...
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System Timing System timing requirements for 100BASE-TX operation are listed in Table 24-2 of Clause 24 of IEEE 802.3. PARAMETER TX_EN Sampled to first bit of “J” on MDI output First bit of “J” on MDI input to CRS ...
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ANALOG ELECTRICAL CHARACTERISTICS 100BASE-TX Transmitter PARAMETER Peak Output Amplitude (|Vp+|, |Vp-|) (see note below) Output Amplitude Symmetry Output Overshoot Rise/Fall time (tr, tf) Rise/Fall time Imbalance Duty Cycle Distortion Jitter Note: Measured at the line side of the transformer. Test ...
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Receiver PARAMETER Signal Detect Assertion Threshold Signal Detect De-assertion Threshold Differential Input Resistance Jitter Tolerance (pk-pk) Baseline Wander Tracking Signal Detect Assertion Time Signal Detect De-assertion Time 10BASE-T Transmitter The Manchester-encoded data pulses, the link pulse and the start-of-idle ...
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Transmitter (Informative) The specifications in the following table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. PARAMETER Output return loss Output Impedance Balance Peak Common-mode Output Voltage ...
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Page 78Q2123 7 78Q2133 Ap pplication Diagra am for 78Q2123/ /78Q2133 © 2009 Teridian Semiconductor Corporatio on 78Q21 123/78Q2133 M MicroPHY™ 10/1 100BASE-TX T Transceiver Rev 1.5 ...
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ISOLATION TRANSFORMERS Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common- mode chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer characteristics: NAME Turns Ratio Open-Circuit Inductance Leakage Inductance ...
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External XTLP Oscillator Characteristics PARAMETER SYMBOL XTLP Input Level XTLN Input Low Voltage XTLP Frequency f XTLP Period Tclkper XTLP Duty Cycle Rise / Fall Time Tr, Tf Absolute Jitter Note 1: IEEE 802.3 frequency tolerance ±50 ppm Page: 35 ...
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PACKAGE PIN DESIGNATIONS (Top View) MDIO MDC LED1 LED0 RXD3 RXD2 RXD1 RXD0 Note: For information only, actual package outline will vary depending on package type. Page TERIDIAN 4 78Q2123 5 78Q2133 6 7 ...
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MECHANICAL SPECIFICATIONS – Dimensions pin - QFN TOP VIEW 0.2 MIN. 0.35 / 0.45 Page 2.5 3.0 / 3.2 0.18 / 0.3 1.5 ...
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RECOMMENDED PCB LAND PATTERN DIMENSIONS 32 Pin - QFN Recommended PCB Land Pattern Dimensions SYMBOL Note 1: Do not place unmasked vias in region denoted by dimension “d”. Note 2: Soldering of bottom internal ...
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TQFP 1.05 MAX 0.15 MAX MECHANICAL SPECIFICATIONS (CONTINUED) Page 7.00 0.22+/-0.05 0.22+/-0.05 0.50 TOP VIEW 0.20 MIN. 1.00 REF. SIDE VIEW © 2009 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver 7.00 0.25 0.60+/-0.15 Rev 1.5 ...
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TQFP Page 78Q2123/78Q2133 MicroPHY™ 5.00 2.50 BOTTOM VIEW © 2009 Teridian Semiconductor Corporation 10/100BASE-TX Transceiver 2.50 5.00 Rev 1.5 ...
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RECOMMENDED PCB LAND PATTERN DIMENSIONS (mm) 32-pin TQFP Recommended PCB Land Pattern Dimensions SYMBOL Page DESCRIPTION MIN Lead pitch © 2009 Teridian Semiconductor Corporation 78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver TYP ...
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... Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com Page Order Number 78Q2123/F 78Q2123R/F 78Q2123CGV/F 78Q2123CGVR/F 78Q2133/F 78Q2133R/F Comments Final Data Sheet release 1. On page 12, changed MR[0.13] description for auto-negotiation mode 2. On page 12, changed MR[0.8] description for auto-negotiation mode 3. On page 22, changed MR[24.6] & ...