71M6521DE TERIDIAN [Teridian Semiconductor Corporation], 71M6521DE Datasheet - Page 22

• Manufacturer Part Number: 71M6521DE
• Description: Energy Meter IC
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

FLSHCRL
WDI
INTBITS
Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated
op-codes is contained in the 71M6521 Software User’s Guide (SUG).
UART
The 71M6521DE/FE includes a UART (UART0) that can be programmed to communicate with a variety of AMR modules. A
second UART (UART1) is connected to the optical port, as described in the optical port description.
Page: 22 of 101
INT0…INT6
0xB2
0xE8
0xF8
© 2005-2008 TERIDIAN Semiconductor Corporation
Table 12: Special Function Registers
R/W
R/W
R/W
R/W
W
W
R
R
Bit 0 (FLSH_PWE): Program Write Enable:
(default).
DPTR.
This bit is automatically reset after each byte written to flash. Writes
to this bit are inhibited when interrupts are enabled.
Bit 1 (FLSH_MEEN): Mass Erase Enable:
Must be re-written for each new Mass Erase cycle.
Bit 6 (SECURE):
Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and
may only be set. Attempts to write zero are ignored.
Bit 7 (PREBOOT):
Indicates that the preboot sequence is active.
The multi-purpose register WDI contains the following bits:
Bit 0 (IE_XFER): XFER Interrupt Flag:
This flag monitors the XFER_BUSY interrupt. It is set by hardware
and must be cleared by the interrupt handler
Bit 1 (IE_RTC): RTC Interrupt Flag:
This flag monitors the RTC_1SEC interrupt. It is set by hardware and
must be cleared by the interrupt handler
Bit 7 (WD_RST): WD Timer Reset:
Read: Reads the PLL_FALL interrupt flag
Write 0: Clears the PLL_FALL interrupt flag
Write 1: Resets the watch dog timer
Interrupt inputs. The MPU may read these bits to see the input to
external interrupts INT0, INT1, up to INT6. These bits do not have
any memory and are primarily intended for debug use
0 – MOVX commands refer to XRAM Space, normal operation
1 – MOVX @DPTR,A moves A to Program Space (Flash) @
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Only byte operations on the whole WDI register
should be used when writing. The byte must have all
bits set except the bits that are to be cleared.
71M6521DE/71M6521FE
Energy Meter IC
DATASHEET
JANUARY 2008
v1.0