AGLP030-V2VQG289I ACTEL [Actel Corporation], AGLP030-V2VQG289I Datasheet

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AGLP030-V2VQG289I

Manufacturer Part Number
AGLP030-V2VQG289I
Description
IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
Manufacturer
ACTEL [Actel Corporation]
Datasheet
December 2008
© 2008 Actel Corporation
IGLOO PLUS Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
Feature Rich
Reprogrammable Flash Technology
In-System Programming (ISP) and Security
Table 1-1 • IGLOO PLUS Product Family
IGLOO PLUS Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
4,608-Bit Blocks
Secure (AES) ISP
FlashROM Bits
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
Maximum User I/Os
Package Pins
Notes:
1. AGLP060 in CS201 does not support the PLL.
2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low-Power Active FPGA Operation
• Flash*Freeze
• Configurable Hold Previous State, Tristate, HIGH, or LOW
• Easy Entry To / Exit From Ultra-Low-Power Flash*Freeze Mode
• 30 k to 125 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 212 User I/Os
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
• FlashLock
† The AGLP030 device does not support this feature.
CS
VQ
Consumption while Maintaining FPGA Content
State per I/O in Flash*Freeze Mode
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
®
to Secure FPGA Contents
2
Technology
1
Enables
Ultra-Low
Power
CS201, CS289
AGLP030
VQ128
High-Performance Routing Hierarchy
Advanced I/O
Clock Conditioning Circuit (CCC) and PLL
Embedded Memory
30 k
256
792
120
1 k
• Segmented, Hierarchical Routing and Clock Structure
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—4 Banks per Chip on All
• Single-Ended
• Selectable Schmitt Trigger Inputs
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Small-Footprint Packages across the IGLOO
• Six CCC Blocks, One with an Integrated PLL
• Configurable
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
• True Dual-Port SRAM (except ×18)
5
6
4
IGLOO
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
PLUS Family
Capabilities, and External Feedback
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
®
PLUS Devices
CS201, CS289
Phase
I/O
AGLP060
VQ176
1,584
60 k
512
Yes
157
1 k
10
18
18
4
1
4
Standards:
Shift,
Multiply/Divide,
LVTTL,
CS281, CS289
AGLP125
125 k
1,024
3,120
212
Yes
1 k
16
36
18
8
1
4
LVCMOS
v1.3
Delay
®
I

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AGLP030-V2VQG289I Summary of contents

Page 1

... VQ Notes: 1. AGLP060 in CS201 does not support the PLL. 2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125. † The AGLP030 device does not support this feature. December 2008 © 2008 Actel Corporation High-Performance Routing Hierarchy • Segmented, Hierarchical Routing and Clock Structure Advanced I/O • ...

Page 2

... When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by one. Table 1-2 • Package Dimensions Package Length × Width (mm/mm) 2 Nominal Area (mm ) Pitch (mm) Height (mm AGLP030 AGLP060 Single-Ended I/Os 120 – 120 101 – CS201 CS281 CS289 8 × ...

Page 3

... Speed Grade F = 20% Slower than Standard* Blank = Standard Supply Voltage 1.5 V only Part Number AGLP030 = 30,000 System Gates AGLP060 = 60,000 System Gates AGLP125 = 125,000 System Gates Notes: 1. Marking information: IGLOO PLUS V2 devices do not have a V2 marking, but IGLOO PLUS V5 devices are marked accordingly. 2. The DC and switching characteristics for the – ...

Page 4

... Commercial temperature range Commercial temperature range: 0°C to 70°C ambient temperature Industrial temperature range: –40°C to 85°C ambient temperature. Contact your local Actel representative for device availability: http://www.actel.com/company/contact/default.aspx AGLP030 AGLP060 – – ...

Page 5

... IGLOO PLUS devices have up to 125 k system gates, supported with kbits of true dual-port SRAM and up to 212 user I/Os. The AGLP030 devices have no PLL or RAM support. Flash*Freeze Technology The IGLOO PLUS device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low-power Flash*Freeze mode ...

Page 6

... FPGA with nonvolatile flash programming can offer. IGLOO PLUS devices (except AGLP030) utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOO PLUS devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard ...

Page 7

... Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOO PLUS devices via an IEEE 1532 JTAG interface. † The AGLP030 device does not support PLL or SRAM. IGLOO PLUS Low-Power Flash FPGAs † † ...

Page 8

... Decryption* FlashRom * Not supported by AGLP030 devices Figure 1-1 • IGLOO PLUS Device Architecture Overview with Four I/O Banks (AGLP030, AGLP060, and AGLP125) Flash*Freeze Technology The IGLOO PLUS device has an ultra-low-power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. ...

Page 9

... The FlashROM is written using the standard IGLOO PLUS IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in AGLP030 devices security keys stored in the FlashROM for a user design. ...

Page 10

... Each member of the IGLOO PLUS family contains six CCCs. One CCC (center west side) has a PLL. The AGLP030 device does not have a PLL or CCCs; it contains only inputs to six globals. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL ...

Page 11

Exceptional tolerance to input period jitter—allowable input jitter 1.5 ns (for PLL only) • Four precise phases; maximum misalignment between adjacent phases × 250 MHz / f (for PLL only) OUT_CCC Global Clocking ...

Page 12

IGLOO PLUS Device Family Overview I/Os with Advanced I/O Standards The IGLOO PLUS family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V). IGLOO PLUS FPGAs ...

Page 13

... Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information ...

Page 14

Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management ...

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