RT9644 RICHTEK [Richtek Technology Corporation], RT9644 Datasheet - Page 15

• Manufacturer Part Number: RT9644
• Description: ACPI Regulator/Controller for Dual Channel DDR Memory Systems
• Manufacturer: RICHTEK [Richtek Technology Corporation]

where T
upper MOSFET respectively. R
simultaneously considered to minimize power loss of upper
MOSFET.
The power loss of lower MOSFET consists of conduction
loss, reverse recovery loss of body diode, and conduction
loss of body diode and is expressed as :
where T
Special control scheme is adopted to minimize body diode
conducting time. As a result, the R
the power loss of lower MOSFET. Use MOSFET with
adequate R
thermal requirements.
MOSFET Selection of LDO
The main criteria for selection of the LDO pass transistor
is package selection for efficient removal of heat.
Select a package and heatsink that maintains the junction
temperature below the rating with a maximum expected
ambient temperature.
The power dissipated in the linear regulator is:
P
where I
is the nominal output voltage of LDO
Layout Consideration
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability. First, place the PWM power stage components.
Mount all the power components and connections in the
top layer with wide copper areas. The MOSFETs of Buck,
DS9644/A-01 August 2007
P
P
UPPER
LOWER
D
I
I
2
2
= I
2
OUT
OUT
1
V
IN
I
OUT(MAX)
OUT
OUT(MAX)
RISE
DIODE
(T
R
R
P
P
RISE
DS(ON)
DS(ON)
COND_UPPER
and T
COND_LOWER
V
DS(ON)
F
is the conducting time of lower body diode.
x (V
is the maximum output current and V
T
FALL
T
DIODE
IN
to minimize power loss and satisfy
FALL
D
(1
- V
are rising and falling time of V
-
OUT
D)
)
2
1
I
f
OUT
)
f
OSC
P
OSC
P
Q
SW_UPPER
RR
RR
DS(ON)
P
DS(ON)
V
DIODE
IN
and QG should be
f
OSC
loss dominates
Preliminary
DS
(10)
(11)
OUT
of
inductor, and output capacitor should be as close to each
other as possible. This can reduce the radiation of EMI
due to the high frequency current loop. If the output
capacitors are placed in parallel to reduce the ESR of
capacitor, equal sharing ripple current should be
considered.
Place the input capacitor directly to the drain of high-side
MOSFET. The MOSFETs of linear regulator should have
wide pad to dissipate the heat. In multilayer PCB, use
one layer as power ground and have a separate control
signal ground as the reference of the all signal. To avoid
the signal ground is effect by noise and have best load
regulation, it should be connected to the ground terminal
of output. Furthermore, follows below guide lines can get
better performance of IC :
(1). The IC needs a bypassing ceramic capacitor as a R-C
filter to isolate the pulse current from power stage and
supply to IC, so the ceramic capacitor should be placed
adjacent to the IC.
(2). Place the high frequency ceramic decoupling close
to the power MOSFETs.
(3). The feedback part should be placed as close to IC as
possible and keep away from the inductor and all noise
sources.
(4). The components of bootstraps should be closed to
each other and close to MOSFETs.
(5).The PCB trace from Ug and Lg of controller to
MOSFETs should be as short as possible and can carry
1A peak current.
(6). Place all of the components as close to IC as possible.
(7).VTT LDO must dissipate heat generated,the pin29
should be connected to the internal ground plane through
four vias.
Below PCB gerber files are our test board for your
reference :
RT9644/A
www.richtek.com
15