ADUM1410 AD [Analog Devices], ADUM1410 Datasheet - Page 6

• Manufacturer Part Number: ADUM1410
• Description: Quad-Channel Digital Isolators
• Manufacturer: AD [Analog Devices]

ADuM1410/ADuM1411/ADuM1412
Parameter
1
2
3
4
5
6
7
8
9
10
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t
measured from the 50% level of the rising edge of the V
t
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
CM
Input enable time is the duration from when V
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (See Table 10).
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
within the recommended operating conditions.
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
PHL
PSK
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
For All Models
H
propagation delay is measured from the 50% level of the falling edge of the V
is the magnitude of the worst-case difference in t
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
Common-Mode Transient Immunity
Refresh Rate
Input Enable Time
Input Disable Time
Input Dynamic Supply Current per Channel
Output Dynamic Supply Current per Channel
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
Opposing-Directional Channels
Change vs. Temperature
Codirectional Channels
at Logic High Output
at Logic Low Output
DD1
and V
9
9
DD2
supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
8
8
6
PLH
7
− t
PHL
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
|
5
7
DISABLE
is set low until the output states are guaranteed to match the input states in the absence of any input data logic
PHL
or t
Ix
10
10
signal to the 50% level of the rising edge of the V
PLH
Symbol
PWD
t
t
t
t
|CM
|CM
t
t
I
I
that is measured between units at the same operating temperature, supply voltages, and output load
DDI (D)
DDO (D)
PSK
PSKCD
PSKOD
R
ENABLE
DISABLE
/t
F
H
L
|
|
Rev. E | Page 6 of 20
Min
25
25
Ix
signal to the 50% level of the falling edge of the V
Typ
5
2.5
35
35
1.1
2.0
5.0
0.07
0.02
O
> 0.8 V
Max Unit
5
30
5
6
DD2
Ox
. CM
signal.
ns
ps/°C
ns
ns
ns
ns
kV/μs
kV/μs
Mbps
μs
μs
mA/Mbps
mA/Mbps
L
is the maximum common-mode voltage slew rate
Test Conditions
C
C
C
C
C
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
V
V
L
L
L
L
L
L
Ix
Ix
IA
IA
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
, V
, V
= V
= 0 V, V
IB
IB
Ox
DD1
, V
, V
signal. t
IC
IC
/V
, V
, V
CM
DD2
ID
ID
= 1000 V,
, V
= 0 or V
= 0 or V
PLH
CM
propagation delay is
DISABLE
= 1000 V,
DD1
DD1
is set high