AT17C010-10 ATMEL Corporation, AT17C010-10 Datasheet
AT17C010-10
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AT17C010-10 Summary of contents
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... FPGA Configuration 2 E PROM Memory 512K and 1M AT17C512 AT17LV512 AT17C010 AT17LV010 Rev. 0944A-A–12/97 1 ...
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Controlling The High-Density AT17 Series Serial EEPROMs Most connections between the FPGA device and the Serial EEPROM are simple and self-explanatory: • The DATA output of the high-density AT17 Series drives DIN of the FPGA devices. • The master FPGA ...
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Pin Configurations 20 PLCC Name I/O 2 DATA I/O 4 CLK I 5 WP1 I 6 RESET/ WP2 GND 14 CEO READY O 17 SER_EN ...
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FPGA Master Serial Mode Summary The I/O and logic functions of the FPGA and their associ- ated interconnections are established by a configuration program. The program is loaded either automatically upon power up command, depending on the state ...
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DC Characteristics Commercial / 5V CC Symbol Description V High-level input voltage IH V Low-level input voltage IL V High-level output voltage ( Low-level output voltage ( High-level output voltage (I OH ...
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AC Characteristics AC Characteristics When Cascading AT17C/LV512/010 6 ...
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AC Characteristics for AT17C512/010 Commercial / Symbol Description ( Data Delay OE ( Data Delay CE (2) T CLK to Data Delay CAC (2) T Data ...
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AC Characteristics for AT17LV512/010 V = 3.3V 10% CC Symbol Description ( Data Delay OE ( Data Delay CE (2) T CLK to Data Delay CAC T Data Hold From CE, OE, or CLK ...
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... Ordering Information - 5V Devices Memory Size Ordering Code 512K AT17C512-10JC AT17C512-10JI 1M AT17C010-10JC AT17C010-10JI Ordering Information - 3.3V Devices Memory Size Ordering Code 512K AT17LV512-10JC AT17LV512-10JI 1M AT17LV010-10JC AT17LV010-10JI 20J 20 Lead, Plastic J-Leaded Chip Carrier (PLCC) Package 20J 20J 20J 20J Package 20J 20J 20J 20J ...