AT17C010-10 ATMEL Corporation, AT17C010-10 Datasheet - Page 3

• Manufacturer Part Number: AT17C010-10
• Description: FPGA Configuration E2PROM Memory
• Manufacturer: ATMEL Corporation

Pin Configurations
Absolute Maximum Ratings*
Operating Temperature .................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground ............................ -0.1V to V
Supply Voltage (V
Maximum Soldering Temp. (10 s @ 1/16 in.)..................260°C
ESD (R
PLCC
20
10
14
15
17
20
2
4
5
6
7
8
ZAP
RESET/OE
= 1.5K, C
SER_EN
READY
Name
DATA
GND
WP1
WP2
CEO
CLK
V
CE
A2
CC
CC
) .........................................-0.5V to +7.0V
ZAP
= 100 pF)............................... 2000V
I/O
I/O
O
O
I
I
I
I
I
I
I
Description
Three-state DATA output for reading. Input/Output pin for programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WRITE PROTECT (1). Used to protect portions of memory during programming. See
programming guide for details.
RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and
RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the
address and bit counters. The logic polarity of this input is programmable as either RESET/OE
or RESET/OE. This document describes the pin as RESET/OE.
WRITE PROTECT (2). Used to protect portions of memory during programming. See
programming guide for details.
Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data
output driver. A High level on CE disables both the address and bit counters and forces the
device into a low power mode. Note this pin will not enable/disable the device in 2-wire Serial
Programming mode (i.e., when SER_EN is Low).
Ground pin.
Chip Enable Out output. This signal is asserted Low on the clock cycle following the last bit
read from the memory. It will stay Low as long as CE and OE are both Low. It will then follow
CE until OE goes High. Thereafter, CEO will stay High until the entire PROM is read again and
senses the status of RESET polarity.
Device selection input, A2. This is used to enable (or select) the device during programming,
when SER_EN is Low (see Programming Guide for more details)
Open collector reset state indicator. Driven Low during power-up reset, released when power-
up is complete. (Recommend a 4.7K
Serial enable is normally high during FPGA loading operations. Bringing SER_EN Low,
enables the two wire serial interface mode for programming.
+3.3V/+5V power supply pin.
CC
+ 0.5V
*NOTICE:
Pull-up on this pin if used).
Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Rat-
ings conditions for extended periods of time may
affect device reliability.
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