TC94A04AFD Toshiba Semiconductor, TC94A04AFD Datasheet
TC94A04AFD
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TC94A04AFD Summary of contents
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TC94A04AF/AFD is a single-chip audio Digital Signal Processor, incorporating 4 way stereo analog switch converter converter, and electronic volume for trimming possible to realize many applications, such as sound field control -hall ...
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Ω Ω Ω Ω Ω Ω Ω Ω Σ∆ Σ∆ Ω Ω ...
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Ω Ω Ω Ω Ω Ω Ω Ω Σ∆ Σ∆ Ω Ω ...
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When I2CS = “L”, data can be transmitted or received in Standard Transmission mode. When the CS signal is Low, control from the microcontroller is enabled. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The ...
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The RAMs are set by command data using the IFDI signal. The first byte is a command, which differs for each RAM. The next two bytes contain the start address for the RAM written. The length of the data field ...
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In ACMP mode, the TC94A04AF/AFD does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a ...
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When I2CS = “H”, data can be transmitted or received in I When the CS signal is Low, control from the microcontroller is enabled mode, the CS signal can be used fixed to “L”. The IFCK ...
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The RAMs are set by command data using the IFDI signal. 2 The first byte after the I C address (32h command, which differs for each RAM. The next two bytes contain the start address for each ...
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In ACMP mode, the TC94A04AF/AFD does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in ...
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The following table lists the control commands that can be used from the microcontroller. = µ = ...
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Each command explanation is shown below. *mark in each command explanation table shows the initial value at the time of reset. * ...
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， ， ， ， ， * ， ， ...
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* * ← ← * ← ...
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Data are sent continuously after transmitting the module sequence RAM head address (2 bytes). Enable a sequential write to RAM. 45h-MSEQ RAM address (2 bytes)-data (2 bytes)-data (2 bytes)-･････････- data (2 bytes) (module sequential RAM: 8 words) ...
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The data written in continuously are sent after transmitting CRAM head address (2 bytes). Enable a sequential write to RAM. 46h-CRAM address (2 bytes)-data (2 bytes)-data (2 bytes)-･････････-data (2 bytes) (CRAM: 384 words) ...
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It is CRAM write-in command which used the address compare mode. A maximum of 32 words is written at once. The data written in continuously are sent after transmitting CRAM head address (2 bytes). Enable a sequential write to ...
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It is ORAM write-in command which used the address compare mode. The data written in continuously are sent after transmitting ORAM head address (2 bytes). Enable a sequential write to RAM. 48h-ORAM address (2 bytes)-data (2 bytes)-data (2 ...
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The data written in continuously are sent after transmitting ORAM head address (2 bytes). Enable a sequential write to RAM. 49h-CRAM address (2 bytes)-data (2 bytes)-data (2 bytes)-･････････-data (2 bytes) (ORAM: 16 words) ...
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= * ･･･ − − * ･･･ − − * ･･･ − − − ･･･ − − − ...
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* ･･･ − − * ･･･ − − = −∞ = × * ･･･ − − − ･･･ − − − − − − − − − − − ...
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The TC94A04AF/AFD supports a self-boot function for setting coefficients and offsets. As Figure 1 shows, the data are set via the microcontroller interface circuit. First saving the data to be set via the microcontroller in the self-boot ROM (SBROM) allows ...
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The following shows the breakdown of the 18 bits. = ...
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Self-boot operation supports two modes: one for use at reset and for setting the microcontroller. To enter this mode, set the RST pin to High or send initialized command. The 2048 fs period (46.4 ms when fs = 44.1 kHz) ...
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After a power-supply injection, once at least, please set up a required register after applying reset which makes RST terminal “L” level and making the value of an internal register decide. In rewriting coefficient data and offset data using ACMP ...
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= = = = − − − − = − = = − ...
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= − = = = × × × × µ − − ...
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+ + + + + → → → → Ω − − − − ...
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= = = = µ − ...
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Standard transmission mode ( CS , IFCK, IFDI, IFDO) ↓ ↓ ↑ ↑ ↑ ↑ ↓ = µ mode ( CS , IFCK, IFDI) ...
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Clock pin (XI) (2) Reset (3) Audio serial interface (ELRI/O, EBCI/O, DIN0 to 2, DOUT) ∼ ...
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Microcontroller interface in standard transmission mode ( CS , IFCK, IFDI, IFDO) (5) Microcontroller interface Purchase of Toshiba I C components conveys a license under the Philips I 2 these components system, ...
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The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba. Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ µ µ µ µ µ µ ...
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The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba. Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ Ω µ µ µ µ µ µ µ ...
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