TC94A04AFG Toshiba Semiconductor, TC94A04AFG Datasheet
TC94A04AFG
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TC94A04AFG Summary of contents
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... TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC94A04AFG,TC94A04AFDG 1 chip Audio Digital Processor TC94A04AFG/AFDG is a single-chip audio Digital Signal Processor, incorporating 4 way stereo analog switch converter converter, and electronic volume for trimming possible to realize many applications, such as sound field control -hall simulation, for example-, digital filter for equalizers, surround, base boost and something ...
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... DSP (I/O Interface) 500 Ω Σ∆ Ch1 DAC circuit Ch2 DAC Circuit DAC 20 kΩ Same as Ch1 DAC circuit TC94A04AFG/AFDG EBCI/O 30 Audio serial interface ELRI/O 29 SYNC 28 GNDR 27 V DDR Delay RAM 26 GNDA4 25 AI4 ...
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... GNDR 38 V DDR 37 Delay RAM NC 36 GNDA4 Ch4 DAC circuit AI4 33 AO4 Same as Ch1 DAC circuit AOT4 30 Ch3 DAC circuit DA34 Ch2 DAC circuit 28 Same as Ch1 DAC circuit AOT3 27 AO3 26 AI3 TC94A04AFG/AFDG BP BP 2005-09-28 ...
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... DIN2 I Note pin (TC94A04AFG): Input level changes TTL/CMOS level by the command (42h: VS). Output is fixed to CMOS level. In case of TC94A04AFDG, pin number are pins and pins. Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to V GND ...
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... GNDAR Analog ground pin for ADC-Rch Note pin (TC94A04AFG): Input level changes TTL/CMOS level by the command (42h: VS). Output is fixed to CMOS level. In case of TC94A04AFDG, pin number are pins and pins. Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to V GND ...
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... GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56 64, 73, 77 pins. Function Master clock is 768 fs. Each master-clock frequency follows. fs 768 fs 32 kHz 24.576 MHz 44.1 kHz 33.868 MHz 48 kHz 36.864 MHz 96 kHz 36.864 MHz ⎯ EBCQS [1:0] Output Frequency 128 fs 3 for test 6 TC94A04AFG/AFDG or DD 2005-09-28 ...
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... RIN1 Omitted 1 Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to V GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56 64, 73, 77 pins. TC94A04AFG/AFDG Function Transmission Mode Toshiba original bus mode bus mode ...
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... When the CS signal is Low, control from the microcontroller is enabled. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC94A04AFG/AFDG loads the IFDI signal on the IFCK signal rising edge. When CS = “H”, the IFCK and IFDI signals are don’t care. ...
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... Therefore, when performing continuously two or more write to word, unless it applies more than 1/fs [sec] per 1 word and it sets up, taking in of data is not performed correctly. At the time of program STOP written in asynchronous. A13 A11 D15 D13 D11 D9 A12 A10 D14 D12 D10 D8 9 TC94A04AFG/AFDG D1 Don’t care D0 Cn: COMMAND An: ADDRESS Dn: Data 2005-09-28 ...
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... C0 A14 In ACMP mode, the TC94A04AFG/AFDG does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example signal flow filter is designed as in the following diagram, unless the data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data ...
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... C mode, the CS signal can be used fixed to “L”. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC94A04AFG/AFDG loads the IFDI data on the IFCK signal rising edge. When CS = “H”, IFCK and IFD signal are don't care. 2.2.1 Setting Registers ...
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... At the time of program STOP written in asynchronous RA7 RA5 RA3 RA15 RA13 RA11 RA9 RA6 RA4 RA2 RA14 RA12 RA10 RA8 12 TC94A04AFG/AFDG HZ HZ end RA1 D15 D13 D11 D9 RA0 D14 D12 D10 D8 Cn: COMMAND 2 An address RAn: RAM-ADDRESS Dn: Data 2005-09-28 ...
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... ACMP mode, the TC94A04AFG/AFDG does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this mode, data must be written to the interface buffer RAM (IFB-RAM). Then, all the data are updated together in a period of 1 fs. For example signal flow filter is designed as in the following diagram, unless the data are batch-updated, the circuit may resonate. The same applies to the K6 to K10 data ...
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... M-RST 4Fh Initialization Note 4: The command which is “Sync” in the transfer Sync with Sync signal needs to set the section to a minimum more until it transmits the follwing command. (It need more than 22.68 µ 44.1 KHz.) TC94A04AFG/AFDG RAM Description Sequential ⎯ ⎯ ...
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... Output ELRI/O pin input divided by 2 (for 96 kHz sampling) ⎯ (Internal fs (Internal fs × (Internal fs × 32 (Internal fs × 64) 1 128 fs (Internal fs × 128 Reserved 15 TC94A04AFG/AFDG EBC- EBC- SYS0 0 ELROS OS1 OS0 Operation ⎯ ...
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... Pads from the beginning 1 Pads from the end 2 I2S format 3 16 TC94A04AFG/AFDG BTA4 BTA3 BTA2 BTA1 BTA0 Operation ⎯ Operation 2005-09-28 ...
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... Pads from the beginning 1 Pads from the end 2 I2S format 3 17 TC94A04AFG/AFDG OSLT OBCS OBCS OFMT OFMT Operation ⎯ ⎯ 2005-09-28 ...
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... Mute OFF 1 * Mute ON 0 Mute OFF 1 * Mute ON 0 Mute OFF 1 * Mute ON 0 Mute OFF 1 * Mute ON ⎯ 0 Disable 1 * Enable 0 2-cycle access 1 * 1-cycle access 0 Does not reset 1 * Reset 0 Does not reset 1 * Reset 18 TC94A04AFG/AFDG ERDET ZST SYRC SYRO Operation ⎯ ⎯ 2005-09-28 ...
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... D10 MSEQ MSEQ MSEQ MSEQ MSEQ Value ⎯ 000h to The data written in module sequence RAM are set up. 3FFh 19 TC94A04AFG/AFDG MSA2 MSA1 MSA0 Operation ⎯ MSEQ MSEQ MSEQ MSEQ MSEQ Operation ⎯ ...
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... D10 CRAM CRAM CRAM CRAM CRAM CRAM D10 Value 7FFFh to Set CRAM data (two-complement-form formula) 8000h 20 TC94A04AFG/AFDG CRAM CRAM CRAM CRAM CRAM Operation ⎯ CRAM CRAM CRAM CRAM ...
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... D10 CRAM CRAM CRAM CRAM CRAM CRAM D10 Value 7FFFh to Set CRAM data (two-complement-form formula) 8000h 21 TC94A04AFG/AFDG CRAM CRAM CRAM CRAM CRAM Operation ⎯ CRAM CRAM CRAM CRAM ...
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... Fh D10 ORAM ORAM ORAM ORAM ORAM ORAM D10 Value ⎯ 000 to Set ORAM data 7FFh 22 TC94A04AFG/AFDG ORAM ORAM ORAM ORAM Operation ⎯ ORAM ORAM ORAM ORAM ORAM D4 D3 ...
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... Fh D10 ORAM ORAM ORAM ORAM ORAM ORAM D10 Value ⎯ 000 to Set ORAM data 7FFh 23 TC94A04AFG/AFDG ORAM ORAM ORAM ORAM Operation ⎯ ORAM ORAM ORAM ORAM ORAM D4 D3 ...
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... Value ⎯ Code : 00h 01h 00h − ATT (dB 1Fh * Initial value: 1Fh ⎯ Code : 00h 01h 00h − ATT (dB 1Fh * Initial value: 1Fh 24 TC94A04AFG/AFDG IFF2 IFF1 IFF0 Operation ⎯ DEMP DEMP 0 0 ...
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... Initial value: 7Fh (level = −∞ ) LEVEL = 20 × log (ATL/128) Code 00h 01h 02h to 00h 0Dh to 7Fh * 1Ah 25h to 3Fh to 7Dh 7Eh 7Fh 25 TC94A04AFG/AFDG ATTS ATTS ATTS ATTS ATTS Operation ⎯ ･･･ 18h 19h ･･･ 1Fh 02h − ...
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... Bit Name Description Initialization from the micro D15 MRST controller command D14 ⎯ to Fixed to 0 (zero) D0 D10 Value 0 * Does not initialize 1 Initializes (set to initial value ( ⎯ 26 TC94A04AFG/AFDG Operation ⎯ 2005-09-28 ...
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... Self-Boot Function Description 4.1 Self-Boot Function The TC94A04AFG/AFDG supports a self-boot function for setting coefficients and offsets. As Figure 1 shows, the data are set via the microcontroller interface circuit. First saving the data to be set via the microcontroller in the self-boot ROM (SBROM) allows various modes to be set later ...
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... Address Address CMD Data CMD Data Data Data Data Data Address Address 28 TC94A04AFG/AFDG (LSB All ‘0’ JMP JMP CMD Data (last) CMD Data (cont) Data (cont) Data (cont) Data (cont) Data (last) JMP 1FFh JMP 1FFh 2005-09-28 ...
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... Boot wait period 2048 fs RST FS BTMODE (internal signal) BootRom Adrs 2 Rom Dt [17:16] JMP BTCSN BTIFCK BTIFDI Figure 3 Boot Timing Chart (at reset) TC94A04AFG/AFDG Wait Period Boot Time (maximum) 64.0 ms 16.0 ms 46.4 ms 11.6 ms 42.7 ms 10.7 ms Boot period 512 fs (max ...
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... Please Do Not Perform Continuation Transmission over the 0th Address. The transmission over the 0th address may incorrect-operate. For example, when writing in 17Fh from 178h and 000h from 007h of CRAM, it must transmit in two steps. 5.4 Please Do Not Set-Up a Soft Reset Command as the Data of Boot ROM. TC94A04AFG/AFDG 30 2005-09-28 ...
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... Power supply voltage Input voltage TC94A04AFG Power dissipation TC94A04AFDG Operating temperature Storage temperature Note 8: Power dissipation of TC94A04AFG is reference value when assembled chip on PCB. (normally 1250 mW.) Electrical Characteristics (unless otherwise specified 25° Characteristics Characteristics Operating power supply voltage Operating frequency range ...
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... I (Note 12) OH2 OH ⎯ (Note 12 OL2 OL (Note 14) ⎯ (Note 13) OL3 OL (Note 12), ⎯ OZ4 OH DD (Note 14) 32 TC94A04AFG/AFDG Min Typ. Max Unit V DD ⎯ ⎯ × 0 ⎯ ⎯ DD × 0 ⎯ ⎯ × 0 ⎯ ⎯ DD × 0.2 ⎯ ...
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... A-Weight, ⎯ S/N d X’tal: 36.864 MHz 20 kHz LPF, ⎯ d X’tal: 36.864 MHz 20 kHz LPF, ⎯ X’tal: 36.864 MHz A-Weight, ⎯ X’tal: 36.864 MHz 33 TC94A04AFG/AFDG Min Typ. Max Unit ⎯ 1.27 1.33 Vrms ⎯ ⎯ k Ω 19 ⎯ ⎯ ⎯ ...
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... EBCI/O input: Unless than 64 EBCI fs ⎯ EBIH ⎯ t EBIL ⎯ LOH L ⎯ DO1 L ⎯ DO2 L 34 TC94A04AFG/AFDG Min Typ. Max Unit ⎯ ⎯ ⎯ ⎯ 13.5 ns ⎯ ⎯ 13.5 ns Min Typ. Max Unit ⎯ ⎯ ⎯ ⎯ ...
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... SCS L ⎯ = 400 ECS L ⎯ = 400 BUF L ⎯ = 400 ⎯ = 400 TC94A04AFG/AFDG Min Typ. Max Unit ⎯ ⎯ µ s 1.0 ⎯ ⎯ µ s 0.2 ⎯ ⎯ µ s 0.25 ⎯ ⎯ µ s 0.25 ⎯ ⎯ µ s 0.25 ⎯ ⎯ µ s 0.5 ⎯ ...
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... Audio serial interface (ELRI/O, EBCI/O, DIN0 to 2, DOUT) t EBIL ELRI/O (I) EBCI/O (I) DIN0 ∼ LIH t EBOL ELRI/O (O) EBCI/O (O) t DOUT LOH t DO1 t t XIH XIL t XI 50% t RRS t EBCI t EBIH t t SDI HDI t EBCO t EBOH t DO2 36 TC94A04AFG/AFDG t WRS t LIH t LOH 2005-09-28 ...
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... Microcontroller interface in standard transmission mode ( CS , IFCK, IFDI, IFDO) RST CS t STB t t CCD WLC CS IFCK IFDI t SCD IFDO t DDO (5) Microcontroller interface BUF IFDI IFCK t t SCH R t WHC t HCD 2 C mode (IFCK, IFDI TC94A04AFG/AFDG t t CKC WCS SCS F ECS 2005-09-28 ...
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... EBCI/O (O) 30 ELRI/O (O) 29 SYNC 28 GNDR DDR GNDA4 25 AI4 24 AO4 23 AOT4 DA34 AOT3 20 AO3 19 AI3 18 GNDA3 17 VRO2 Analog V DD 2200 pF 2200 pF Analog GND 10 kΩ 10 kΩ AOT3 AOT4 (L2 out) (R2 out) TC94A04AFG/AFDG Digital V DD GND Digital GND 2005-09-28 ...
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... V 28 DA34 AOT3 27 AO3 26 AI3 4.7 µF (BP) 0.1 µF 47 µF Analog V 2200 pF 2200 pF 2200 pF Analog GND 10 kΩ 10 kΩ 10 kΩ AOT2 AOT3 AOT4 (R1 out) (L2 out) (R2 out) TC94A04AFG/AFDG MCU I/F Digital GND Digital GND 2005-09-28 ...
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... Package Dimensions Weight: 1.08 g (typ.) (Note) Palladium plate 40 TC94A04AFG/AFDG 2005-09-28 ...
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... Package Dimensions Weight: 1.57 g (typ.) TC94A04AFG/AFDG (Note) Palladium plate it 2005-09-28 ...
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... TC94A04AFG/AFDG 42 2005-09-28 ...