XR2211 Exar Corporation, XR2211 Datasheet - Page 6

• Manufacturer Part Number: XR2211
• Description: FSK Demodulator/ Tone Decoder
• Manufacturer: Exar Corporation

PRINCIPLES OF OPERATION
Signal Input (Pin 2): Signal is AC coupled to this
terminal. The internal impedance at pin 2 is 20K .
Recommended input signal level is in the range of 10mV
rms to 3V rms.
Quadrature Phase Detector Output (Pin 3): This is the
high impedance output of quadrature phase detector and
is internally connected to the input of lock detect voltage
comparator. In tone detection applications, pin 3 is
connected to ground through a parallel combination of R
and C
detect outputs. If the tone detect section is not used, pin 3
can be left open.
Lock Detect Output, Q (Pin 6): The output at pin 6 is at
“low” state when the PLL is out of lock and goes to “high”
state when the PLL is locked. It is an open collector type
output and requires a pull-up resistor, R
proper operation. At “low” state, it can sink up to 5mA of
load current.
Lock Detect Complement, (Pin 5): The output at pin 5 is
the logic complement of the lock detect output at pin 6.
This output is also an open collector type stage which can
sink 5mA of load current at low or “on” state.
FSK Data Output (Pin 7): This output is an open collector
logic stage which requires a pull-up resistor, R
proper operation. It can sink 5mA of load current. When
decoding FSK signals, FSK data output is at “high” or “off”
state for low input frequency, and at “low” or “on” state for
high input frequency. If no input signal is present, the logic
state at pin 7 is indeterminate.
FSK Comparator Input (Pin 8): This is the high
impedance input to the FSK voltage comparator.
Normally, an FSK post-detection or data filter is
connected between this terminal and the PLL phase
detector output (pin 11). This data filter is formed by R
and C
comparator is set by the internal reference voltage, V
available at pin 10.
Reference Voltage, V
biased at the reference voltage level, V
- 650mV. The DC voltage level at this pin forms an internal
reference for the voltage levels at pins 5, 8, 11 and 12. Pin
XR-2211
Rev. 3.01
D
F
(see Figure 3 ) to eliminate the chatter at lock
(see Figure 3. ) The threshold voltage of the
REF
(Pin 10): This pin is internally
REF
: V
L
, to V
REF
L
, to V
= V
CC
CC
CC
REF
for
for
/2
D
F
,
6
10 must be bypassed to ground with a 0.1 F capacitor for
proper operation of the circuit.
Loop Phase Detector Output (Pin 11): This terminal
provides a high impedance output for the loop phase
detector. The PLL loop filter is formed by R
connected to pin 11 (see Figure 3. ) With no input signal, or
with no phase error within the PLL, the DC level at pin 11 is
very nearly equal to V
available at the phase detector output is equal to 2 x V
VCO Control Input (Pin 12): VCO free-running
frequency is determined by external timing resistor, R
connected from this terminal to ground. The VCO
free-running frequency, f
where C
For optimum temperature stability, R
range of 10K
This terminal is a low impedance point, and is internally
biased at a DC level equal to V
current drawn from pin 12 must be limited to < 3mA for
proper operation of the circuit.
VCO Timing Capacitor (Pins 13 and 14): VCO
frequency is inversely proportional to the external timing
capacitor, C
Figure 6. ) C
200pF to 10 F.
VCO Frequency Adjustment: VCO can be fine-tuned by
connecting a potentiometer, R
(see Figure 10. )
VCO Free-Running Frequency, f
have a separate VCO output terminal. Instead, the VCO
outputs are internally connected to the phase detector
sections of the circuit. For set-up or adjustment purposes,
the VCO free-running frequency can be tuned by using
the generalized circuit in Figure 3 , and applying an
alternating bit pattern of O’s and 1’s at the known mark
and space frequencies. By adjusting R
then be tuned to obtain a 50% duty cycle on the FSK
output (pin 7). This will ensure that the VCO f
accurately referenced to the mark and space frequencies.
0
is the timing capacitor across pins 13 and 14.
0
0
, connected across these terminals (see
must be non-polar, and in the range of
to 100K
f
O
REF
. The peak to peak voltage swing
O
R
(see Figure 9. )
, is:
0
1
· C
X
0
REF
, in series with R
Hz
. The maximum timing
O
: XR-2211 does not
0
0
must be in the
, the VCO can
O
1
0
at pin 12
value is
and C
REF
0
1
.
,