HT82K68 Holtek Semiconductor Inc, HT82K68 Datasheet - Page 11

• Manufacturer Part Number: HT82K68
• Description: Multimedia Keyboard Encoder OTP
• Manufacturer: Holtek Semiconductor Inc

Interrupt
The HT82K68E provides an internal timer
counter interrupt. The interrupt control regis-
ter (INTC;0BH) contains the interrupt control
bits to set not only the enable/disable status but
also the interrupt request flags.
Once an interrupt subroutine is serviced, all
other interrupts will be blocked (by clearing the
EMI bit). This scheme may prevent any further
interrupt nesting. Other interrupt requests may
occur during this interval but only the interrupt
request flag is recorded. If a certain interrupt re-
quires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC
may be set to allow interrupt nesting. If the
stack is full, the interrupt request will not be ac-
knowledged, even if the related interrupt is en-
abled, until the SP is decremented. If immediate
service is desired, the stack must be prevented
from becoming full.
All these kinds of interrupt have the wake-up
capability. As an interrupt is serviced, a control
transfer occurs by pushing the program counter
onto the stack followed by a branch to a subrou-
tine at the specified location in the program
Labels
C
AC
Z
OV
PD
TO
¾
¾
Bits
0
1
2
3
4
5
6
7
C is set if the operation results in a carry during an addition operation or if a bor-
row does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or if
no borrow from the high nibble into the low nibble in subtraction; otherwise AC
is cleared.
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD is cleared when either a system power-up or executing the CLR WDT in-
struction. PD is set by executing the HALT instruction.
TO is cleared by a system power-up or executing the CLR WDT or HALT in-
struction. TO is set by a WDT time-out.
Undefined, read as "0"
Undefined, read as "0"
Preliminary
Status register
11
memory. Only the program counter is pushed
onto the stack. If the contents of the register and
Status register (STATUS) are altered by the in-
terrupt service program which corrupt the de-
sired control sequence, the contents should be
saved in advance.
The internal timer counter interrupt is initialized
by setting the timer counter interrupt request
flag (T0F; bit 5 of INTC), which is normally
caused by a timer counter overflow. When the in-
terrupt is enabled, and the stack is not full and
the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag
(T0F) will be reset and the EMI bit cleared to dis-
able further interrupts.
During the execution of an interrupt subroutine,
other interrupt acknowledgements are held un-
til the RETI instruction is executed or the EMI
bit and the related interrupt control bit are set to
1 (if the stack is not full). To return from the in-
terrupt subroutine, a RET or RETI instruction
may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
Interrupts occurring in the interval between
the rising edges of two consecutive T2 pulses,
Function
HT82K68E
August 8, 2000