ISPLSI2064E-135LT100 Lattice Semiconductor, ISPLSI2064E-135LT100 Datasheet - Page 7

• Manufacturer Part Number: ISPLSI2064E-135LT100
• Description: In-System Programmable SuperFAST High Density PLD
• Manufacturer: Lattice Semiconductor

Derivations of
Note: Calculations are based upon timing specifications for the ispLSI 2064E-200L.
ispLSI 2064E Timing Model
GOE 0,1
Ded. In
Y0,1,2
I/O Pin
Reset
(Input)
t
t
t
su
h
co
3.1ns
3.4ns
7.9ns
I/O Delay
=
=
=
=
=
=
=
=
=
=
=
=
#21
#20
t
su,
Logic + Reg su - Clock (min)
(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.5 + 0.6 + 2.9) + (1.2) - (0.5 + 0.6 + 1.0)
Clock (max) + Reg h - Logic
(
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.6 + 4.0) + (2.3) - (0.5 + 0.6 + 2.9)
Clock (max) + Reg co + Output
(
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 1.6)
I/O Cell
t
t
t
io +
io +
io +
t
h and
t
t
t
grp +
grp +
grp +
t
t
t
co from the Product Term Clock
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
io +
Reg 4 PT Bypass
t
orp +
t
XOR Delays
#33, 34,
Control
PTs
#25, 26, 27
grp +
Feedback
t
grp +
20 PT
35
#24
t
Comb 4 PT Bypass #23
ob)
7
t
OE
ptck(min))
RE
CK
Table 2- 0042A-2064e
t
20ptxor)
Specifications ispLSI 2064E
GLB
GLB Reg Bypass
D
RST
GLB Reg
Delay
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
0491/2064
#38,
39
I/O Cell
(Output)
I/O Pin