AM79C90 Advanced Micro Devices, AM79C90 Datasheet
AM79C90
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AM79C90 Summary of contents
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... Completely software- and hardware-compatible with AMD’s LANCE device (Am7990) (see Appendix A) to provide the user with a complete interface module for an Ethernet network. The Am79C90 is designed using a scalable CMOS technology and is compatible with a variety of microprocessors. On-board DMA, advanced buffer management, and extensive error reporting and diagnostics facilitate design and improve system performance ...
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... DAL9 21 A22 DAL10 22 A23 DAL11 23 RX DAL12 24 RENA CLSN RCLK TENA TCLK 17881B-2 Am79C90 (HIMIB ) PLCC ADR 56 READY 55 RESET ...
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... Am79C90 Am7992B C-LANCE SIA AUI DTE Cable Am79C90 Am7992B C-LANCE SIA DTE Am79C90 Am7992B C-LANCE SIA MAU—Medium Attachment Unit Am79C90 MAU TAP Am7996 Transceiver Power Supply Ethernet Coax Am7996 Transceiver RG58A/U or RG58C/U BNC “T” Power Supply MAU Am79C98 Am79C100 ...
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... J = 68-Pin Plastic Leaded Chip Carrier (PL 068) SPEED Not Applicable Valid combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C90 Valid Combinations ...
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... When BYTE = H (indicating a byte transfer) the table in- dicates on which part of the 16-bit data bus the actual data will appear. Whenever byte swap is activated, the only data that is swapped is data traveling to and from the Transmit/ Receive FIFOs. Am79C90 0 BM Selection LOW Whole Word ...
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... CSR0 status flags is set: BABL, MERR, MISS, RINT, TINT or IDON. INTR is enabled by bit 06 of CSR0 (INEA = 1). INTR remains asserted until the source of Interrupt is removed. RCLK Receive Clock (Input MHz square wave synchronized to the Receive data and only active while receiving an Input Bit Stream. Am79C90 ...
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... TX Transmit (Output) Transmit Output Bit Stream Power Supply Pin + recommended that 0.1 F and 10 F decoupling capacitors be used between Ground Pin 1 and 24 (48-Pin DlPs) should be connected together externally, as close to the chip as possible. Am79C90 and ...
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... The C-LANCE is pin-for- pin compatible with AMD’s LANCE device (Am7990). Please refer to Appendix B for a complete comparison between the C-LANCE and LANCE devices. Address Bits 16–23 Control A16–A23 Buffer ALE A16–A23 Am79C90 C-LANCE DAL0 – DAL15 ALE ADR Latch CS Decoder 17881B-5 ...
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... This mode can be useful if sending packets to all of a particular type of de- vice simultaneously (i.e., send a packet to all file servers or all printer servers). Additional details on logical ad- dressing can be found in the INITIALIZATION section Am79C90 AMD Data/Address Bits 0-15 ALE Address ...
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... These include a CRC check and two loop back modes (internal/external). Errors may be introduced into the system to check error detection logic. A Time Domain Reflectometer is incorporated into the C-LANCE to aid system designers in locating faults in the Ethernet physi- cal medium. Shorts and opens manifest themselves in reflections which are sensed by the TDR. Am79C90 ...
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... Receive Descriptor for Nth Data Buffer Transmit Data Buffer #1 Transmit Data Buffer #2 Transmit Data Buffer #3 Transmit Data Buffer #N Receive Data Buffer #1 Receive Data Buffer #2 Receive Data Buffer #3 Receive Data Buffer #N Figure 2-1. C-LANCE/Processor Memory Interface Am79C90 AMD Initialization Block Transmit Descriptor Ring (4 words per entry) Receive ...
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... BYTE signal is decoded along with the least significant ad- dress bit to determine upper or lower byte explicit scheme in which two signals labeled as BYTE MASK (BM0 and BM1) indicate which byte is addressed. When Am79C90 Receive Buffer Data Packet 1 ...
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... Transfers are a minimum of 600 ns in length ex- cept for the first transfer of a bus mastership period in which the minimum is 700 ns. Transfers can be in- creased in 100 ns increments. Am79C90 AMD 13 ...
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... There are two types of delays which depend on which internal register is accessed. Type 1 refers to access of CSR0, CSR3 and RAP. Type 2 refers to access of CSR1 and CSR2 which are longer than Type 1 delay See Note 1 Figure 3. Bus Slave Read Timing Am79C90 Read Data O.D. 17881B-9 ...
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... The write cycle is similar to the read cycle except that the DAL00 – DAL15 lines change from containing ad- dresses to data after either ALE or AS goes inactive. After data is valid on the bus, DAS goes active. Data to memory is held valid after DAS goes inactive. Refer to Figure 5-2. Am79C90 AMD O.D. 17881B-10 15 ...
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... READY DAL0–DAL15 (Read) DALO (Read) DALI (Read) READ (Read) Figure 5-1. Bus Master Read Timing (Single DMA Cycle 200 300 400 Address, BM0, BM1 Address Am79C90 WAIT T5 T6 700 500 600 O.D. Data In 17881B-11 ...
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... DAL0–DAL15 (Write) DALO (Write) DALI (Write) READ (Write) Figure 5-2. Bus Master Write Timing (Single DMA Cycle 100 200 300 400 Address, BM0, BM1 Address Am79C90 T WAIT 500 600 700 Data Out AMD O.D. 17881B-12 17 ...
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... IEEE 802.3 at the physical layer include the following: End of Transmission State Common Mode Voltage Common Mode Current Less than 1 mA Receive , Collision Input Threshold Fault Protection Am79C90 IEEE 802.3 Ethernet Half Step Full Step (Rev 1) or Half Step (Rev 2) 5 – ...
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... HOST device. Once enabled, the C-LANCE has the ability to access memory locations to acquire additional operating parameters. The Am79C90 has the ability to do independent buffer management as well as transfer data packets to and from the Ethernet. There are three memory structures accessed by the Chip: Initialization Block— ...
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... TDMD 12 MISS TXON RXON INEA INTR 17881B-15 Am79C90 Description BABBLE is a transmitter timeout er- ror. It indicates that the transmitter has been on the channel longer than the time required to send the maxi- mum length packet. BABL is a flag which indicates ex- cessive length in the transmit buffer. ...
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... Bit Name TXON = 0, RXON 06 05 RXON 04 TXON Am79C90 AMD Description INTR INTERRUPT FLAG is set by the “ORing” of BABL, MISS, MERR, RINT, TINT and IDON. If INEA = 1 and INTR = 1, the INTR pin will be LOW. INTR is READ ONLY; writing this bit has no effect. INTR is cleared by ...
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... Control and Status Register 2 (CSR2) READ/WRITE: 15 must be reloaded Bit Name 15:08 07:00 IADR 0 during 0 0 Am79C90 Accessible only when the STOP bit 0 of CSR is a ONE and RAP = 01. The C-LANCE preserves the con- 1 tents of CSR after STOP IADR (15:01) 17881B-16 Description The low order 15 bits of the address of the first word (lowest address) in the Initialization Block ...
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... The Mode Register allows alteration of the C-LANCE’s operating parameters. Normal operation is with the Mode Register clear ALE Asserted HIGH Asserted LOW and cleared by BM HOLD 1 0 Am79C90 AMD TLEN–TDR (23:16) IADR +22 TDRA (15:00) IADR +20 RLEN–RDRA (23:16) IADR +18 RDRA (15:00) IADR +16 LADRF (63:48) IADR +14 LADRF (47:32) IADR +12 LADRF (31:16) IADR +10 LADRF (15:00) IADR +08 ...
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... LOOPBACK No loopback, normal External Internal 3 ). Am79C90 Description COLL FORCE COLLISION. This bit allows the collision logic to be tested. The C-LANCE must be in internal loop- back mode for COLL to be valid. If COLL = 1, a collision will be forced during the subsequent transmission attempt. This will result in 16 total ...
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... Later, when a packet is received, the driver first looks at the Individual/Group bit of the destination address of the packet to find out whether or not this is a multicast ad- dress is, the driver must search the multicast ad- dress list to see if this address is in the list not in the list, the packet is discarded. Am79C90 AMD 25 ...
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... Logical Address 02:00 Filter Transmit Descriptor Ring Pointer Match 17881B-22 31: Boundary)’ 17881B-23 28:24 23:03 02:00 Am79C90 Name Description RLEN RECEIVE RING LENGTH is the number of entries in the receive ring expressed as a power of two. RLEN Number of Entries ...
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... LADR is written by the host and is not changed by the C-LANCE Receive Message Descriptor 1 (RMD1) 15 Bit Name 15 OWN 14 ERR 13 FRAM 0 17881B-25 Am79C90 AMD HADR ENP STP BUFF CRC OFLO FRAM ERR OWN 17881B-26 Description This bit indicates that the descriptor entry is owned by the host (OWN = the C-LANCE (OWN = 1) ...
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... Bit Name 15:00 LADR Transmit Message Descriptor 1 (TMD1 BCNT Must be Ones 17881B-27 Am79C90 0 MCNT RES 17881B-28 RESERVED. Read as zeroes. Write as zeroes. MESSAGE BYTE COUNT is the length in bytes of the received mes- sage. MCNT is valid only when ERR is clear and ENP is set. MCNT is writ- ten by the chip and cleared by the host ...
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... This field is written by the host and is not changed by the C-LANCE Transmit Message Descriptor 2 (TMD2) 15 Bit 15:12 11:00 indicates that the Am79C90 AMD 12 11 17881B-31 Name Description ONES Must be ones. This field is set by the host and is not changed by the C-LANCE. BCNT ...
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... Transmit FIFO (see Figure 8-1). The C-LANCE does this lookahead only once does not own the next transmit Descriptor Table Entry (DTE) (2nd TX ring Am79C90 RETRY ERROR indicates that the transmitter has failed in 16 attempts to successfully transmit a message due to repeated collisions on the me- dium ...
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... Transmit FIFO are interleaved with burst transfers from the Receive FIFO. By interleaving the transmit buffer transfers with the receive buffer transfers, the beginning of the transmit packet is preloaded in the Transmit FIFO, ready to be transmitted immediately following the end of the receive packet on the wire. Am79C90 AMD 31 ...
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... Byte alignment can be reversed by set- ting the Byte Swap (BSWP) bit in CSR3. TRANSMISSION – WORD READ FROM EVEN MEM- ORY ADDRESS BSWP=0: BSWP=1: TRANSMISSION – BYTE READ FROM EVEN MEMORY ADDRESS Am79C90 or Receive FIFO and DAL FIFO BYTE n gets DAL <07:00> ...
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... The C-LANCE can handle dribbling bits when a received packet terminates; the input to the C-LANCE, RCLK, stops following the deassertion of RENA. During the reception, the CRC is generated on every serial bit (including the dribbling bits) coming from the medium, Am79C90 AMD Dest. Source Type ...
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... If there is a late collision (colli- sion occurring after 64 byte times), the C-LANCE will not attempt to transmit this packet again; it will terminate the transmission, note the LCOL error in TMD3, and trans- mit the next packet in the ring. Am79C90 ...
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... In internal loopback, the packets should be ad- dressed to the node itself. In external loopback, multicast addressing can be used only when DTCR = the mode register. In this case, the user needs to append the CRC bytes. Loopback is controlled by bits <06, 03, 02> INTL, DTCR, and LOOP of the MODE register. Am79C90 AMD 35 ...
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... Source Address and Length field are part of the data which are transparent to the C-LANCE. Reception is indicated at the input pin by the assertion of RENA and the presence of clock on RCLK while TENA is inactive. The C-LANCE does not sample the received data until about 800 ns after RENA goes high. Am79C90 ...
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... Operating ranges define those limits between which the func- tionality of the device is guaranteed. Test Conditions IOL = 3.2 mA IOH = –0.4 mA VIN = 0 VCC and I load applied Test Conditions MHz MHz MHz Am79C90 AMD . . . . . . . . . . . . . . . . . + +4. +5. Commercial Min Typ Max Unit 0.8 V ...
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... TCT (Note 7) 2t TCT (Note 1) 6t TCT Am79C90 Typ Max Unit 101 118 ...
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... Test Conditions Min 0 10 200 35 (CSR0, CSR3, RAP) (Note 6) (CSR1, 2) (Note 120 70 200 135 0 55 110 Am79C90 AMD Typ Max Unit TCT 12t ns TCT 130 ns ns 250 ...
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... Test Conditions Min 0 0 (Note (CSR0, CSR3, RAP) (Notes 4, 6) (CSR1, 2) (Note (Note TCT (RCLK Period) = 100 ns, t RCT . TCT Am79C90 Typ Max Unit TCT 14t ns TCT 100 ns 75 ...
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... 100 pF A. Normal and Three-State Outputs 100 pF B. Open-Drain Outputs (INTR, HOLD/BUSRQ, READY) Am79C90 17881B- 1.5 V 17881B-38 AMD 41 ...
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... Changing from from Don’t Care, Changing, Any Change State Permitted Unknown Center Does Not Apply Line is High- Impedance “Off” State 20 Serial Link Timing (Collision Serial Link Timing (Receive) Am79C90 KS000010 17881B- 17881B-40 ...
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... RESET is an asynchronous input to the C-LANCE and is not part of the Bus Acquisition timing. When RESET is asserted, the C-LANCE becomes a Bus Slave after the transmission is completed by the C-LANCE. 3 Serial Link Timing (Transmit) Drivers Enabled 24 Bus Acquisition Timing Am79C90 AMD 17881B-41 O.D. 21 17881B-42 43 ...
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... Type 1 refers to access of CSR0 CSR3 and RAP. Type 2 refers to access of CSR1 and CSR2 which are longer than Type 1 delay See Note Bus Slave Read Timing Am79C90 Read Data O 17881B-45 ...
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... SWITCHING WAVEFORMS DAL0–DAL15 DAS Read READY (Output from C-LANCE) 74 HOLD CS ADR Write Data Bus Slave Write Timing Am79C90 AMD O 17881B-46 45 ...
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... AMD SWITCHING WAVEFORMS Am79C90 ...
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... SWITCHING WAVEFORMS Am79C90 AMD 47 ...
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... TO NEXT ADDRESS MOV CL,16 ;CL=BIT COUNTER MOV BX,DX ;GET HIGH WORD OF CRC ROL BX,1 ;PUT CRC31 TO LSB XOR BX,BP ;COMBINE CRC31 WITH INCOMING BIT SAL AX,1 ;LEFT SHIFT CRC ACCUMULATOR RCL DX,1 AND BX,0001H ;BX=CONTROL BIT JZ SETH30 ;DO NOT XOR IF CONTROL BIT = 0 PERFORM XOR OPERATION WHEN CONTROL BIT= 1 Am79C90 ...
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... HASH CODE ALREADY ZERO MOV CL,3 ;DIVIDE HASH CODE BY 8 SHR BL,CL ;TO GET TO THE CORRECT BYTE MOV AL,01H ;PRESET FILTER BIT AND AH,7H ;EXTRACT BIT COUNT MOV CL,AH SHL AL,CL ;SHIFT BIT TO CORRECT POSITION OR [Dl + BX],AL ;SET IN HASH FILTER POP BP POP DX POP CX POP BX POP AX RET ENDS END Am79C90 AMD 49 ...
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... REM PERFORM CRC ALGORITHM ON ARRAY A(0–47) 560 REM 570 FOR 31: C( NEXT I 580 FOR 590 REM SHIFT CRC REGISTER BY 1 600 FOR STEP –1: C(l) = C(I–1): NEXT I 610 C( 620 T = C(32) XOR A(N): REM T = CONTROL BIT 630 THEN 700: REM JUMP IF CONTROL BIT=0 50 Am79C90 ...
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... Ethernet address */ ladrf[8], /* Logical address filter */ CRC[33], /* CRC register, 1 word/bit + extra control bit */ poly CRC polynomial. poly[n] = coefficient of the x**n term of the CRC generator polynomial. */ {1,1,1,0, 1,1,0,1, 1,0,1,1, 1,0,0,0, 1,0,0,0, 0,0,1,1, 0,0,1,0, 0,0,0,0 }; void main() Am79C90 AMD 51 ...
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... The hash code is the 6 least significant bits of the CRC in reverse order: CRC[0] = hash[5], CRC[1] = hash[4], etc. */ hashcode = 0; for (i=0; i<6; i++) hashcode = (hashcode << CRC[i]; /* Bits 3–5 of hashcode point to byte in address filter. Bits 0–2 point to bit within that byte. */ byte = hashcode >> Am79C90 ...
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... CRC and control bit (CRC[32]) */ for (j=32; j>0; j––) CRC[j] = CRC[j–1]; CRC[ bit XOR (control bit set CRC = CRC XOR polynomial (bit ^ CRC[32]) for (j=0; j<32; j++) CRC[j] ^= poly[j]; } Am79C90 AMD 53 ...
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... Am79C90 LAF Destination Bit Address Accepted ...
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... APPENDIX B Comparison Between C-LANCE (Am79C90) and LANCE (Am7990) Devices OVERVIEW The Am79C90 C-LANCE device is a pin-for-pin equiv- alent for the Am7990 LANCE device. Using an ad- vanced 0.8-micron CMOS process, the C-LANCE device consumes less power than the LANCE device, which is implemented in an outdated NMOS process. ...
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... RX Descriptor Zero Buffer Unpredictable results when the RX Byte Count Handling Descriptor Buffer Byte Count is set to zero. 56 Am79C90 C-LANCE 50 mA transmit 6 s 500 ns is set, the slave cycle is allowed to complete before the C-LANCE resets. when the STOP bit is set to one. ...
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... C-LANCE device from the LANCE device. The LANCE device writes bit 13 of TMD1 to zero when updating transmit status in the transmit descriptor. The C-LANCE device will write this bit with the value read set to one it will be returned as a one. Am79C90 ADD_FCS FCS Added? X Yes X ...
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... IEEE 802.3 specifications state that the Signal Quality Error (SQE) test window should be at least 4.0 s and no more than 8.0 s. The LANCE device implements window, which is not compliant with this specification. This generally turns out non-issue because 802.3 also specifies that the Am79C90 ...
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... LANCE device can give false CERR indications. As mentioned in 7c), Item 3 is generally a non-issue. 9. Receive Lockup The LANCE device has an erratum in which the re- ceiver locks up when the system bus latency is very high. This erratum is fixed in the C-LANCE device. Am79C90 59 ...
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... The following differences in AC specification exist between the C-LANCE and the LANCE. # maximum TEP # maximum TDP # minimum RDS # minimum RDAS # minimum RDYS Am79C90 C-LANCE LANCE ...
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... Elimination of Burn-In Option The burn-in option for the C-LANCE is no longer avail- able. Thus, the ordering part number Am79C90PCB is no longer valid (see page 4 of the C-LANCE data sheet). 18. RX Descriptor Zero Buffer Byte Count Handling The 12-bit BCNT field in the receive descriptor of the LANCE and C-LANCE devices is loaded with the 2’ ...
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... Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, b IMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet- FAST , PCnet- FAST +, PCnet-Mobile, QFEX, QFEXr, QuASI , QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc ...