AM79C90 Advanced Micro Devices, AM79C90 Datasheet - Page 23

• Manufacturer Part Number: AM79C90
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: Advanced Micro Devices

Control and Status Register 3 (CSR3)
CSR3 allows redefinition of the Bus Master interface.
READ/WRITE:
Bit
15:03
02
01
00
All data transfers from the C-LANCE in the Bus Master
mode are in words. However, the C-LANCE can handle
odd address boundaries and/or packets with an odd
number of bytes.
15
BSWP
ACON
BCON
Name
RES
Accessible only when the STOP bit
of CSR
CSR
setting the STOP bit in CSR
Description
Reserved. Read as zeroes. Write as
zeroes.
BYTE SWAP allows the chip to oper-
ate in systems that consider bits
(15:08) of data to be pointed at an
even address and bits (07:00) to be
pointed at an odd address.
When BSWP = 1, the C-LANCE will
swap the high and low bytes on DMA
data transfers between the Receive
FIFO and bus memory. Only data
from the Receive FIFO transfers is
swapped; the Initialization Block
data and the Descriptor Ring entries
are NOT swapped.
BSWP is READ/WRITE and cleared
by RESET or by setting the STOP bit
in CSR
ALE CONTROL defines the asser-
tive state of ALE when the C-LANCE
is a Bus Master. ACON is READ/
WRITE and cleared by RESET and
by setting the STOP bit in CSR
BYTE CONTROL redefines the Byte
Mask and Hold l/O pins. BCON is
READ/WRITE
RESET or by setting the STOP bit in
CSR
BCON
ACON
0
1
3
0
.
0
1
is cleared by RESET or by
0
0
.
BUSAKO BYTE BUSRQ
is ONE and RAP = 11.
Pin 16 Pin 15 Pin 17
BM
1
and
3
Asserted HIGH
Asserted LOW
2 1
BM
17881B-18
ALE
cleared
0
0
P R E L I M I N A R Y
0
BCON
ACON
BSWP
RES
HOLD
.
0
.
Am79C90
by
Initialization
Initialization Block
Chip initialization includes the reading of the initializa-
tion block in memory to obtain the operating parame-
ters. The following is a definition of the Initialization
Block.
The Initialization Block is read by the C-LANCE when
the INIT bit in CSR0 is set. The INIT bit should be set be-
fore or concurrent with the STRT bit to insure proper pa-
rameter initialization and chip operation. After the
C-LANCE has read the Initialization Block, IDON is set
in CSR0 and an interrupt is generated if INEA = 1.
Higher Address
Base Address of Block MODE
Mode
The Mode Register allows alteration of the C-LANCE’s
operating parameters. Normal operation is with the
Mode Register clear.
15
14
TLEN–TDR (23:16)
TDRA (15:00)
RLEN–RDRA (23:16) IADR +18
RDRA (15:00)
LADRF (63:48)
LADRF (47:32)
LADRF (31:16)
LADRF (15:00)
PADR (47:32)
PADR (31:16)
PADR (15:00)
8
7
6 5
4
3
2 1
IADR +22
IADR +20
IADR +16
IADR +14
IADR +12
IADR +10
IADR +08
IADR +06
IADR +04
IADR +02
IADR +00
17881B-19
AMD
0
DTCR
COLL
DRX
DTX
LOOP
DRTY
INTL
EMBA
RES
PROM
23