AM79C989JCT Advanced Micro Devices, AM79C989JCT Datasheet
AM79C989JCT
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AM79C989JCT Summary of contents
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... Auto-Negotiation and the ability to use various media types. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. ...
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BLOCK DIAGRAM System Interface Jabber Timer QTX_EN Collision Detect QTX_DATA Elasticity FIFO QRX_DATA QRX_VALID QRX_CRS QCLSN SCLK QRST/STRB MDC MDIO 10BASE-T Transceiver 0 Manchester Encoder Manchester Polarity ...
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CONNECTION DIAGRAM QRST/STRB REXT VSS QINT/CI- PCI/CI+ DI- DI+ VSSAUI DO- DO+ VDDTX QuEST ...
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LOGIC DIAGRAM QTX_EN QTX_DATA QRX_DATA QRX_VALID QRX_CRS QCLSN SCLK QRST/STRB MDC V SS MDIO LOGIC SYMBOL QuASI DDIO V DDTX( SSAUI V SSTX(2) V ...
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RELATED PRODUCTS Part No. Am7990 Local Area Network Controller for Ethernet (LANCE) Am7992B Serial Interface Adapter (SIA) Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79C989 J Valid Combinations Am79C989 ...
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TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Auto-Negotiation Next Page Register (Reg 7 ...
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PIN DESIGNATIONS Listed by Pin Number Pin No. Pin Name Pin No. 1 VDDIO 2 QRX_DATA 3 QRX_VALID 4 QTX_DATA 5 QTX_EN 6 SCLK 7 QRST/STRB 8 REXT 9 VSS 10 QINT/CI- 11 PCI/CI+ Listed by Group Pin Number Pin ...
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Pin Number Pin Name QuASI Interface (Continued) 42 QCLSN 43 QRX_CRS Management Interface 40 MDC 41 MDIO Miscellaneous Pins 6 SCLK 7 QRST/STRB 8 REXT Power Pins 1 VDDIO 44 VSSIO 39 VDD 9 VSS 14 VSSAUI 29, 23, 17 ...
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RXD3 10BASE-T Receive Data Port 3 Input RXD3 are the 10BASE-T differential data receivers for port 3. AUI Signal Pins DO AUI Data Out Output When Port 0 is configured for AUI, DO are the AUI dif- ferential data out ...
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Management Interface MDC Management Data Clock Input MDC provides the timing reference for data on the MDIO pin. The Management Interface provides read and write access to QuEST registers, similar to the MII management interface of the IEEE 802.3u standard. ...
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FUNCTIONAL DESCRIPTION Overview The QuEST device is a highly integrated physical layer solution for twisted pair 10-Mbps Ethernet applications. There are three main sets of interfaces to the QuEST. On the network side, there are the 10BASE-T transmit and receive ...
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Receiver The 10BASE-T interface section includes a compliant 10BASE-T receiver which incorporates a low pass filter eliminating the requirement for off-chip filters. The re- ceiver circuit employs squelch circuits programmable to a standard distance of 100 meters and an ...
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The QuEST can be manually configured to support either half-duplex or full-duplex operation. The QuEST device can operate with any remote 10BASE-T standard device or like devices that support the Auto- Negotiation algorithm, including 10/100 Mbps devices. 10BASE-T Algorithm T ...
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Either five or six signal pins are used for the AUI func- tion PCI/CI+; and, if Interrupt is disabled, QINT/CI-. AUI Transmitter The AUI circuit provides a differential transmit circuit which operates at Pseudo Emitter Coupled ...
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QRX_CRS signal is primarily useful for calibrating net- work timers in the external MAC or repeater device. Data which is held in the elasticity FIFO will be delayed. When the QRX_VALID (Receive Data Valid) is asserted in the appropriate slot, ...
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Table 2. QuEST Device Address Designations PHYAD Bits Signals with Pull up Resistors signals QCLSN QRX_VALID QRX_ VALID, QCLSN QRX_DATA 1 ...
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Table 5. Shared Registers REGAD Register Name 2-3 Device ID 16 Interrupt Enable and Status 17 Summary Status Port Registers Nine physical registers in the QuEST device are allo- cated per port. Six of the port registers relate to Auto- ...
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The port can be forced into full duplex operation when both the Duplex_Mode set and the ANEG_EN bit clear. If the ANEG_EN bit is set, this bit is ignored. When the Duplex_Mode is modified, the 8 Duplex_Mode port ...
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Device ID Registers (Reg 2-3) Device ID Registers (Reg 2-3) contain Read/Only (R/O) bits. Registers 2 and 3 designate a unique De- vice ID: the manufacturer ID is designated by Reg 2 bits Bit(s) Name Bits 3-18 of the IEEE ...
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Auto-Negotiation Link Partner Ability Register (Reg 5) The Auto-Negotiation Link Partner Ability Register (Reg 5) describes the advertised ability of the link Bit(s) Name 1 = Link partner next page requested; 15 Next Page 0 = Link partner next page ...
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Auto-Negotiation Expansion Register (Reg 6) The Auto-Negotiation Expansion Register (Reg 6) pro- vides additional information which assists in the Auto- Table 14. Auto-Negotiation Expansion Register (Reg 6) Bit(s) Name 15:4 Reserved Written and read as zero Link partner ...
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Interrupt Status and Enable Register (Reg 16) Interrupt Status and Enable Register (Reg 16) contains Read/Write (R/W), Read/Only (R/O), or Cleared on Table 16. Interrupt Status and Enable Register (Reg 16) Bit(s) Name 15:13 Reserved Written and read as zero. ...
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Summary Status Register (Reg 17) The Summary Status Register (Reg 17 global reg- ister accessible to all ports. This register is Read/Only Table 17. Summary Status Register (Reg 17) Bit(s) Name 1 = Link Status of port 3 ...
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Control Register (Reg 18) The Control Register (Reg 18) configures the port in conjunction with the Auto-Negotiation registers. The Bit(s) Name 1 = 10BASE-T link integrity state machine is forced to the “link good” state; Force Link Good 0 = ...
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Status Register (Reg 19) The Status Register (Reg 19) contains Read/Only (R/ O) and Cleared on Read (COR) bits which indicate Bit(s) Name 15:3 Reserved Written and read as zero Frames received underflowed or overflowed the elasticity FIFO; ...
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SYSTEM APPLICATIONS 10 Mbps Ethernet Switch The QuEST device is targeted for use in 10BASE-T switching applications. The QuEST device provides four 10BASE-T receive and transmit ports. VDD VDD Switch Interface TX_EN TX_DATA RCV_DATA RCV_DV CLSN RCV_CRS SCLK RESET INT ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . .- +150 C Ambient Temperature . . . . . . . . . . . . . . . 0 ...
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Parameter Symbol Parameter Description Attachment Unit Interface (AUI) (continued) Receive Data Differential Input V ATH Threshold CI/DI DI and CI Differential Input V ASQ Threshold (Squelch) DI and CI Differential Mode Input V AIDV Voltage Range V DI and CI ...
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KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from from May Will be ...
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QuASI Interface SCLK QRST/STRB QTX_EN Not Defined QTX_DATA QRX_DATA QRX_VALID QRX_CRS QCLSN Figure 2. QuASI Interface Timing Diagram No. Symbol SCLK Period (40 MHz, 100 ppm MSI1 Not Tested QRST/STRB hold time after rising edgeof SLCK. ...
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Management Interface MDC MDIO Figure 3. Management Interface Timing Diagram No. Symbol 10 t MDC Clock Period. MII0 11 t MDC high pulse. MII1 12 t MDC low pulse. MII2 13 t MDIO setup to rising edge of MDC. MII3 ...
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Fast Link Pulse Timing FLP Burst FLP 20 20 Link Pulse Timing Clock Pulse Data Pulse No. Symbol 20 t Link Pulse Width. FLP0 21 t Clock to Data Delay. FLP1 22 t Clock to Clock ...
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Attachment Unit Interface (AUI) (DI+) – (DI–) VASQ (CI+) – (CI–) VASQ (DO+) – (DO–) No. Symbol Pulse Width Accept/Reject Threshold. PWODI Pulse Width Maintain/Turn-Off Threshold. PWKDI Pulse Width Accept/Reject Threshold. ...
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Interface VTSQ+, VLTSQ+ (RXD+) – (RXD– –) VTSQ–, VLTSQ– VTPOV+ (TXD+) – (TXD–) VTPOV– Figure 6. 10BASE-T Interface Timing Diagram No. Symbol 40 t RXD Frequency Rejection. TP1 41 t RXD High/Low Frequency Time-out. TP2 42 t TXD End ...
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... Copyright 1997 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. QuEST is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...