AM79C989JCT Advanced Micro Devices, AM79C989JCT Datasheet - Page 18

• Manufacturer Part Number: AM79C989JCT
• Description: Quad Ethernet Switching Transceiver (QuEST)
• Manufacturer: Advanced Micro Devices

Interrupt Function
The Interrupt function indicates when there is a change
in the Link Status, Duplex Mode, Auto-Negotiation sta-
tus, MAU Error status, or any combination thereof for
any port. The Interrupt Register (Register 16) contains
the interrupt status and interrupt enable bits. The status
is always updated whether the interrupt enable bits are
set or not. However, if the interrupt enable bits are set
active, the logical OR of the selected bits will drive the
QINT open drain output pin.
When an interrupt occurs, the system will need to poll
the interrupt register to determine the source of the in-
terrupt and to clear the status bits. The individual regis-
ters can be read to determine the exact nature of the
change in status. Individual bits clear on read (COR)
except for the Jabber error, which is a Self-Clearing
(SC) bit when the QuEST device exits the Jabber state.
3.3 Volt Operation
The QuEST device is designed to easily and reliably in-
terface to systems with 3.3 V or 5 V power supplies.
This is accomplished by having a separate power sup-
ply pin, VDDIO, which can be connected to either a 3.3
V or 5 V supply. The only pins affected by the choice of
supply are: QRX_DATA, QRX_VALID, QRX_CRS,
QCLSN, and MDIO.
18
A4
Table 2. QuEST Device Address Designations
0
0
0
0
1
1
1
1
PHYAD Bits
Table 3. Channel Address Designations
A3
A1
0
0
1
1
0
0
1
1
0
0
1
1
PHYAD Bit
A2
0
1
0
1
0
1
0
1
no signals
QRX_VALID
QRX_ VALID, QCLSN
QRX_DATA
QRX_DATA, QCLSN
QRX_DATA, QRX_ VALID
QRX_DATA, QRX_ VALID, QCLSN
QCLSN
A0
Signals with Pull up Resistors
0
1
0
1
Channel Number
0
1
2
3
P R E L I M I N A R Y
Am79C989
The data sheet specification for the QuEST device is
for TTL input and output levels. The QuEST device
meets these specifications, regardless of which supply
voltage is used. The difference made by using a 3.3 V
supply is that the MAXIMUM output voltage on the pins
listed above is guaranteed by design not to exceed
3.3 V.
REGISTER DESCRIPTION
The QuEST device supports nine physical registers per
port plus four registers which are globally shared
among all four ports. In summary, there are 40 registers
available.
Shared Registers
Four registers are globally shared among all four ports:
Registers 2 and 3 designate the Device ID, Register 16
is Interrupt Enable and Status, and Register 17 is Sum-
mary Status. When accessing the shared registers, the
lower two bits of the PHYAD address (bits A1 and A0)
are ignored.
REGAD
8-15
2-3
16
17
18
19
20
0
1
4
5
6
7
Table 4. Register and Port Matrix
Auto Negotiation Next
Auto Negotiation Link
Auto Negotiation
Auto Negotiation
Auto Negotiation
Auto Negotiation
Summary Status
Register Name
Status Change
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Error Mask
Expansion
Device ID
Interrupt
Unused
Control
Partner
Control
Status
Status
Page
00
0
0
0
0
0
0
0
0
0
PHYAD [0:1] /Port
Port Number
01
Unused
1
1
Shared
1
1
1
1
Shared
1
1
1
Shared
10
2
2
2
2
2
2
2
2
2
11
3
3
3
3
3
3
3
3
3