PSD913F1-B-90JI ST Microelectronics, PSD913F1-B-90JI Datasheet - Page 79

• Manufacturer Part Number: PSD913F1-B-90JI
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: ST Microelectronics

Preliminary Information
Microcontroller Interface – PSD9XXFV AC/DC Parameters
(3 V Versions)
Power Down Timing
V
NOTE: 1. Vstbyon is measured at V
Reset Pin Timing
NOTE: 1. RESET will not reset Flash programming/erase cycles.
NOTE: 1. t
stbyon
Symbol
t
t
Symbol
Symbol
t
t
t
t
t
t
BVBH
BXBL
NLNH
OPR
NLNH-PO
NLNH-A
LVDV
CLWH
2. RESET will abort Flash programming or erase cycle.
Timing
CLCL
is the CLKIN clock period.
ALE Access Time from
Power Down
Maximum Delay from APD Enable
to Internal PDN Valid Signal
V stby Detection to V stbyon Output
High
V stby Off Detection to V stbyon
Output Low
Warm RESET Active Low Time (Note 1)
RESET High to Operational Device
Power On Reset Active Low Time
Warm Reset, will abort and reset Flash
programming/erase cycles to Read
mode. For PSD9X4FV only.
(3 V Versions)
Parameter
Parameter
(3 V Versions)
(3 V Versions)
Parameter
CC
ramp rate of 2 ms.
CLKIN Input
Conditions
Using
Conditions
Conditions
(Note 1)
(Note 1)
Min
-12
Max
145
Min
Min
Min
300
25
1
15
-15
*
t
Max
150
CLCL
Typ
Typ
20
20
(µs) (Note 1)
Min
-20
Max
Max
300
PSD9XX Family
Max
200
Unit
Unit
Unit
ms
µs
µs
ns
ns
µs
ns
µs
75