EVAL-AD73360EZ AD [Analog Devices], EVAL-AD73360EZ Datasheet
EVAL-AD73360EZ
Related parts for EVAL-AD73360EZ
EVAL-AD73360EZ Summary of contents
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FEATURES Six 16-Bit A/D Converters Programmable Input Sample Rate Simultaneous Sampling 77 dB SNR 64 kS/s Maximum Sample Rate –83 dB Crosstalk Low Group Delay (25 s Typ per ADC Channel) Programmable Input Gain Flexible Serial Port which Allows ...
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AD73360–SPECIFICATIONS Parameter REFERENCE REFCAP Absolute Voltage, V REFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT Minimum Load Resistance Maximum Load Capacitance ADC SPECIFICATIONS 2, 3 Maximum Input Range at VIN Nominal Reference Level at VIN (0 dBm0) ...
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Parameter LOGIC INPUTS V , Input High Voltage INH V , Input Low Voltage INL I , Input Current Input Capacitance IN LOGIC OUTPUTS V , Output High Voltage Output Low Voltage OL Three-State ...
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AD73360–SPECIFICATIONS Parameter REFERENCE REFCAP Absolute Voltage, V REFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT Minimum Load Resistance Maximum Load Capacitance ADC SPECIFICATIONS 2, 3 Maximum Input Range at VIN Nominal Reference Level at VIN (0 dBm0) ...
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Parameter LOGIC INPUTS V , Input High Voltage INH V , Input Low Voltage INL I , Input Current Input Capacitance IN LOGIC OUTPUTS V , Output High Voltage Output Low Voltage OL Three-State ...
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AD73360 TIMING CHARACTERISTICS Limit at Parameter T = – + Clock Signals 24 24.4 3 Serial Port 0.4 × 0.4 × t ...
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Figure 1. MCLK Timing 100 A TO OUTPUT PIN C L 15pF 100 A Figure 2. Load Circuit for Timing Specifications MCLK SCLK SCLK IS ...
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... SDO 14 15 Model AD73360AR AD73360ASU EVAL-AD73360EB EVAL-AD73360EZ NOTES 0.3' Small Outline IC (SOIC Thin Quad Flatpack IC (TQFP). 2 The AD73360 evaluation board can be interfaced to an ADSP-2181 EZ-KIT Lite Texas Instruments EVM kit. 3 The upgrade consists of a connector for the expansion port P3 of the EZ-KIT Lite ...
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Mnemonic Function VINP1 Analog Input to the Positive Terminal of Input Channel 1. VINN1 Analog Input to the Negative Terminal of Input Channel 1. VINP2 Analog Input to the Positive Terminal of Input Channel 2. VINN2 Analog Input to the ...
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AD73360 TERMINOLOGY Absolute Gain Absolute gain is a measure of converter gain for a known signal. Absolute gain is measured (differentially) with a 1 kHz sine wave at 0 dBm0 for each ADC. The absolute gain specification is used for ...
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FUNCTIONAL DESCRIPTION General Description The AD73360 is a six-channel, 16-bit, analog front end. It comprises six independent encoder channels each featuring signal conditioning, programmable gain amplifier, sigma-delta A/D convertor and decimator sections. Each of these sections is described in further ...
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AD73360 Figure 7 shows the various stages of filtering that are employed in a typical AD73360 application. In Figure 7a we see the trans- fer function of the external analog antialias filter. Even though single RC pole, ...
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Serial Port (SPORT) The AD73360s communicate with a host processor via the bidirectional synchronous serial port (SPORT) which is compat- ible with most modern DSPs. The SPORT is used to transmit and receive digital data and control information. Multiple AD73360s ...
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AD73360 SPORT Register Maps There are eight control registers for the AD73360, each eight bits wide. Table V shows the control register map for the AD73360. The first two control registers, CRA and CRB, are reserved for controlling the SPORT. ...
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CONTROL REGISTER A RESET Bit Name CONTROL REGISTER Bit Name CONTROL REGISTER C 5VEN Bit Name 0 ...
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AD73360 CONTROL REGISTER D PUI2 Bit Name CONTROL REGISTER E PUI4 Bit Name CONTROL REGISTER F PUI6 Bit Name ...
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CONTROL REGISTER G SEEN Bit Name CONTROL REGISTER H INV Bit Name REGISTER BIT DESCRIPTIONS Control Register A CRA:0 Data/Program Mode. This bit controls ...
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AD73360 Control Register C CRC:0 Global Power-Up. Writing this bit will cause all six channels of the AD73360 to power-up regardless of the status of the Power Control Bits in CRD-CRF. If less than six channels are ...
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Master Clock Divider The AD73360 features a programmable master clock divider that allows the user to reduce an externally available master clock, at pin MCLK, by one of the ratios pro- duce an ...
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AD73360 Resetting the AD73360 The RESET pin resets all the control registers. All registers are reset to zero indicating that the default SCLK rate (DMCLK/8) and sample rate (DMCLK/2048) are at a minimum to ensure that slow speed DSP engines ...
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INTERFACING The AD73360 can be interfaced to most modern DSP engines using conventional serial port connections and an extra enable control line. Both serial input and output data use an accompa- nying frame synchronization signal which is active high one ...
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AD73360 SE SCLK SDOFS UNDEFINED DATA SDO SDIFS CONTROL WORD SDI Figure 15a. Interface Signal Timing for Program Mode Operation (Writing to a Register) SE SCLK SDOFS SDO UNDEFINED DATA SDIFS SDI REGISTER READ INSTRUCTION Figure 15b. Interface Signal Timing ...
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Cascade Operation The AD73360 has been designed to support up to eight devices in a cascade connected to a single serial port (see Figure 17). The SPORT interface protocol has been designed so that device addressing is built into the ...
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AD73360 SE SIGNAL SYNCHRONIZED DSP CONTROL TO MCLK 1/2 74HC74 MCLK CLK RESET SIGNAL SYNCHRONIZED DSP CONTROL TO MCLK TO RESET D Q 1/2 74HC74 CLK MCLK Figure 19. SE and RESET Sync Circuit for Cascaded ...
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Figure 23 shows a comparison of SNR results achieved by vary- ing either the Decimation Rate Setting or the DMCLK Rate Settings. 81 DMCLK = MCLK ...
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AD73360 Digital Interface As there are a number of variations of sample rate and clock speeds that can be used with the AD73360 in a particular appli- cation important to select the best combination to achieve the desired ...
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DSP SPORT Interrupts If SPORT interrupts are enabled important to note that the active signals on the frame sync pins do not necessarily corre- spond with the positions in time of where SPORT interrupts are generated. On ADSP-21xx ...
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AD73360 Programming a Single AD73360 for Data Mode Operation This section describes a typical sequence in programming a single AD73360 to operate in normal Data Mode. It details the control (program) words that are sent to the device to configure ...
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Programming a Single AD73360 for Mixed Mode Operation This section describes a typical sequence in programming a single AD73360 to operate in Mixed Mode. The device is con- figured in Nonframe Sync Loop-Back (see Figure 14), which allows the DSP’s ...
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AD73360 Configuring a Cascade of Two AD73360s to Operate in Data Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73360s to set them up for operation not ...
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DSP Tx REG CONTROL WORD 1 1000 1001 0000 0011 STEP 1 DSP Tx REG CONTROL WORD 1 1000 0001 0000 0011 STEP 2 DSP Tx REG CONTROL WORD 2 1000 1010 1110 0001 STEP 3 DSP Tx REG CONTROL ...
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AD73360 Configuring a Cascade of Two AD73360s to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73360s to configure them for operation in Mixed Mode. It ...
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DSP Tx REG CONTROL WORD 1 1000 1001 0000 0011 STEP 1 DSP Tx REG CONTROL WORD 2 1000 0001 0001 0011 STEP 2 DSP Tx REG CONTROL WORD 2 1000 0001 0001 0011 STEP 3 DSP Tx REG CONTROL ...
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AD73360 Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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REV. A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Small Outline IC (R-28) 0.7125 (18.10) 0.6969 (17.70 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) SEATING 0.0125 (0.32) (1.27) ...