NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 119

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NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
Functional Description
5.5.1.1
LPC Cycle Types
The ICH7 implements the following cycle types as described in
Table 5-5.
LPC Cycle Types Supported
Cycle Type
I/O Read
I/O Write
DMA Read
(Desktop and
Mobile Only)
DMA Write
(Desktop and
Mobile Only)
Bus Master Read
Bus Master Write
NOTES:
1.
Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer
can be to any address. However, the 2-byte transfer must be word-aligned (i.e., with an
address where A0=0). A dword transfer must be dword-aligned (i.e., with an address
where A1 and A0 are both 0)
5.5.1.2
Start Field Definition
Table 5-6.
Start Field Bit Definitions
Bits[3:0]
Encoding
0000
Start of cycle for a generic target
0010
Grant for bus master 0
0011
Grant for bus master 1
Stop/Abort: End of a cycle for a
1111
target.
NOTE: All other encodings are RESERVED.
®
Intel
ICH7 Family Datasheet
Comment
®
1 byte only. Intel
ICH7 breaks up 16- and 32-bit processor cycles into
multiple 8-bit transfers.
1 byte only. ICH7 breaks up 16- and 32-bit processor cycles into multiple
8-bit transfers.
Can be 1, or 2 bytes
Can be 1, or 2 bytes
Can be 1, 2, or 4 bytes. (See Note 1 below)
Can be 1, 2, or 4 bytes. (See Note 1 below)
Definition
Table 5-5
119

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