NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 610

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NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
15.1.21
IDE_TIMS — IDE Secondary Timing Register
(IDE—D31:F1)
Address Offset: 42h
Default Value:
0000h
Bit
IDE Decode Enable (IDE) — R/W. This bit enables/disables the Secondary decode.
The IDE I/O Space Enable bit (D31:F1:04h, bit 0) in the Command register must be
set in order for this bit to have any effect. Additionally, separate configuration bits are
provided (in the IDE I/O Configuration register) to individually disable the secondary
IDE interface signals, even if the IDE Decode Enable bit is set.
15
0 = Disable.
1 = Enables the Intel
and Control Block (376h). Accesses to these ranges return 00h, as the secondary
channel is not implemented.
No Operation (NOP) — R/W. These bits are read/write for legacy software
14:12
compatibility, but have no functionality in the ICH7 since a secondary channel does not
exist.
11
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software
10:0
compatibility, but have no functionality in the ICH7 since a secondary channel does not
exist.
15.1.22
SLV_IDETIM—Slave (Drive 1) IDE Timing Register
(IDE—D31:F1) (Desktop and Mobile Only)
Address Offset: 44h
Default Value:
00h
Bit
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
7:4
but have no functionality in the Intel
Primary Drive 1 IORDY Sample Point (PISP1) — R/W. This field determines the
number of PCI clocks between IOR#/IOW# assertion and the first IORDY sample point,
if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is
set.
3:2
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Primary Drive 1 Recovery Time (PRCT1) — R/W. This field determines the
minimum number of PCI clocks between the last IORDY sample point and the IOR#/
IOW# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the IDE
timing register for primary is set.
1:0
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
610
43h
Attribute:
Size:
Description
®
ICH7 to decode the associated Command Blocks (170–177h)
Attribute:
Size:
Description
®
ICH7.
IDE Controller Registers (D31:F1)
R/W
16 bits
R/W
8 bits
®
Intel
ICH7 Family Datasheet

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