Microcontrollers (MCU) OTP EPROM 4K SPI

ST62T65CN6

Manufacturer Part NumberST62T65CN6
DescriptionMicrocontrollers (MCU) OTP EPROM 4K SPI
ManufacturerSTMicroelectronics
ST62T65CN6 datasheet
 


Specifications of ST62T65CN6

Processor SeriesST62T6xCoreST6
Data Bus Width8 bitProgram Memory TypeEPROM
Program Memory Size3884 BData Ram Size128 B
Interface TypeSCIMaximum Clock Frequency8 MHz
Number Of Programmable I/os21Number Of Timers1
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 125 C
Mounting StyleSMD/SMTPackage / CaseSSOP-28
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / Rohs Status Details  
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8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI
3.0 to 6.0V Supply Operating Range
8 MHz Maximum Clock Frequency
-40 to +125°C Operating Temperature Range
Run, Wait and Stop Modes
5 Interrupt Vectors
Look-up Table capability in Program Memory
Data Storage in Program Memory:
User selectable size
Data RAM: 128 bytes
Data EEPROM: 128 bytes (none on ST62T55C)
User Programmable Options
21 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
8 I/O lines can sink up to 30mA to drive LEDs or
TRIACs directly
8-bit Timer/Counter with 7-bit programmable
prescaler
8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
Digital Watchdog
Oscillator Safe Guard
Low Voltage Detector for Safe Reset
8-bit A/D Converter with 13 analog inputs
8-bit Synchronous Peripheral Interface (SPI)
On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
User configurable Power-on Reset
One external Non-Maskable Interrupt
ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
July 2001
ST62T55C
ST62T65C/E65C
PDIP28
PS028
SS0P28
CDIP28W
(See end of Datasheet for Ordering Information)
DEVICE SUMMARY
OTP
EPROM
DEVICE
(Bytes)
(Bytes)
ST62T55C
3884
ST62T65C
3884
ST62E65C
3884
EEPROM
-
-
-
128
128
Rev. 2.9
1/86

ST62T65CN6 Summary of contents

  • Page 1

    OTP/EPROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table ...

  • Page 2

    ST62T55C ST62T65C/E65C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...

  • Page 3

    ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    ST62P55C ST62P65C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62T55C, ST62T65C and ST62E65C devic- es are low cost members of the ST62xx 8-bit HC- MOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on ...

  • Page 6

    ST62T55C ST62T65C/E65C 1.2 PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS OSCin and OSCout. These pins are ...

  • Page 7

    MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Figure 3Memory Addressing Diagram PROGRAM SPACE 0000h PROGRAM ...

  • Page 8

    ... U.V. erasure that also results into the whole EPROM context erasure. Note: Once the Readout Protection is activated longer possible, even for STMicroelectronics, to gain access to the OTP contents. Returned parts with a protection set can therefore not be ac- cepted. ...

  • Page 9

    MEMORY MAP (Cont’d) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space com- prises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and ...

  • Page 10

    ST62T55C ST62T65C/E65C MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat- ed anywhere in program memory, ...

  • Page 11

    MEMORY MAP (Cont’d) 1.3.6 Data RAM/EEPROM (DRBR) Address: E8h — Write only 7 DRBR - - - - 4 Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit ...

  • Page 12

    ST62T55C ST62T65C/E65C MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as ...

  • Page 13

    MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, ...

  • Page 14

    ST62T55C ST62T65C/E65C 1.4 PROGRAMMING MODES 1.4.1 Option Bytes The two Option Bytes allow configuration capabili the MCUs. Option byte’s content is automati- cally read, and the selected options enabled, when the chip reset is activated. It can only ...

  • Page 15

    PROGRAMMING MODES (Cont’d) 1.4.2 EPROM Erasing The EPROM of the windowed package of the MCUs may be erased by exposure to Ultra Violet light. The erasure characteristic of the MCUs is such that erasure begins when the memory is ex- ...

  • Page 16

    ST62T55C ST62T65C/E65C 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and ...

  • Page 17

    CPU REGISTERS (Cont’d) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the ad- dress of ...

  • Page 18

    ST62T55C ST62T65C/E65C 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ...

  • Page 19

    CLOCK SYSTEM (Cont’d) Turning on the main oscillator is achieved by re- setting the OSCOFF bit of the A/D Converter Con- trol Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the oscillator start up ...

  • Page 20

    ST62T55C ST62T65C/E65C CLOCK SYSTEM (Cont’d) Figure 9. OSG Filtering Principle (1) (2) (3) (4) (1) Maximum Frequency for the device to work correctly (2) Actual Quartz Crystal Frequency at OSCin pin (3) Noise from OSCin (4) Resulting Internal Frequency Figure ...

  • Page 21

    CLOCK SYSTEM (Cont’d) Oscillator Control Registers Address: DCh — Write only Reset State: 00h 7 OSCR - - - - 3 Bit 7-4. These bits are not used. Bit 3. Reserved. Cleared at Reset. Must be kept cleared. Bit 2. ...

  • Page 22

    ST62T55C ST62T65C/E65C CLOCK SYSTEM (Cont’d) Figure 11. Clock Circuit Block Diagram MAIN OSCILLATOR Figure 12. Maximum Operating Frequency (f Maximum FREQUENCY (MHz 2.5 3 Notes this area, operation is guaranteed ...

  • Page 23

    RESETS The MCU can be reset in four ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. – by Low Voltage Detection (LVD) 3.2.1 RESET Input ...

  • Page 24

    ST62T55C ST62T65C/E65C RESETS (Cont’d) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will ...

  • Page 25

    RESETS (Cont’d) 3.2.6 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (locat program ROM starting at address 0FFEh). A jump to the beginning of ...

  • Page 26

    ST62T55C ST62T65C/E65C RESETS (Cont’d) Table 5Register Reset Status Register Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control AR TIMER Mode Control Register AR TIMER Status/Control 0 Register AR ...

  • Page 27

    DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset ...

  • Page 28

    ST62T55C ST62T65C/E65C DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register This register is set to 0FEh on ...

  • Page 29

    DIGITAL WATCHDOG (Cont’d) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110 Bit Watchdog Control bit If the hardware option is selected, this bit is forced ...

  • Page 30

    ST62T55C ST62T65C/E65C DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of ...

  • Page 31

    INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction to the associated ...

  • Page 32

    ST62T55C ST62T65C/E65C INTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know ...

  • Page 33

    INTERRUPTS (Cont’d) 3.4.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed ...

  • Page 34

    ST62T55C ST62T65C/E65C INTERRUPTS (Cont’d) Figure 21Interrupt Block Diagram FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE V DD PORT A PBE PORT B Bits PORT C PBE Bits SPIDIV Register SPINT bit SPIE bit SPIMOD Register AR TIMER TIMER1 V ...

  • Page 35

    POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following ...

  • Page 36

    ST62T55C ST62T65C/E65C POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the ...

  • Page 37

    ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt – Input with ...

  • Page 38

    ST62T55C ST62T65C/E65C I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters ...

  • Page 39

    I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe transitions are illustrated ...

  • Page 40

    ST62T55C ST62T65C/E65C I/O PORTS (Cont’d) Table 11I/O Port Option Selections MODE AVAILABLE ON PA0-PA7 Input PB0-PB5, PB6-PB7 PC0-PC4 PA0-PA7 Input PB0-PB5, PB6-PB7 with pull up PC0-PC4 Input PA0-PA7 with pull up PB0-PB5, PB6-PB7 PC0-PC4 with interrupt PA0-PA7 Analog Input PC0-PC4 ...

  • Page 41

    I/O PORTS (Cont’d) 4.1.3 Timer 1 Alternate function Option When bit TOUT of register TSCR1 is low, pin PC1/ Timer 1 is configured through the port registers as any standard pin of Port addition connect- ed ...

  • Page 42

    ST62T55C ST62T65C/E65C I/O PORTS (Cont’d) Figure 24Peripheral Interface Configuration of SPI, Timer 1 and AR Timer PC3/Sout PC2/Sin PC4/SCK PC1/TIM1 ARTIMin ARTIMout 42/ PP/OD 1 MUX 0 REGISTER MUX 0 1 MUX 0 DR PP/OD ...

  • Page 43

    TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 The peripheral may be configured in three different operating modes. Figure 25 shows the ...

  • Page 44

    ST62T55C ST62T65C/E65C TIMER (Cont’d) 4.2.1 Timer Operating Modes There are three operating modes, which are se- lected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to the ...

  • Page 45

    TIMER (Cont’d) 4.2.3 Application Notes The user can select the presence of an on-chip pull-up on the TIMER pin as option. TMZ is set when the counter reaches zero; howev- er, it may also be set by writing 00h in ...

  • Page 46

    ST62T55C ST62T65C/E65C 4.3 AUTO-RELOAD TIMER The Auto-Reload Timer (AR Timer) on-chip pe- ripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as ...

  • Page 47

    AUTO-RELOAD TIMER (Cont’d) Figure 27. AR Timer Block Diagram f INT M f 7-Bit /3 U INT AR PRESCALER X PS0-PS2 CC0-CC1 PB6/ ARTIMin SL0-SL1 EF SYNCHRO DATA BUS 8 AR COMPARE REGISTER 8 CPF COMPARE 8 OVF 8-Bit LOAD ...

  • Page 48

    ST62T55C ST62T65C/E65C AUTO-RELOAD TIMER (Cont’d) It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTI- Mout, the contents of the ...

  • Page 49

    AUTO-RELOAD TIMER (Cont’d) Capture Mode with PWM Generation. In this mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter is incremented on every clock rising edge. An 8-bit capture operation from ...

  • Page 50

    ST62T55C ST62T65C/E65C AUTO-RELOAD TIMER (Cont’d) 4.3.3 AR Timer Registers AR Mode Control Register (ARMC) Address: D5h — Read/Write Reset status: 00h 7 TCLD TEN PWMOE EIE CPIE The AR Mode Control Register ARMC is used to program the different operating ...

  • Page 51

    AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1) Address: D7h — Read/Write 7 PS2 PS1 PS0 D4 SL1 Bist 7-5 = PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine the Prescaler divi- sion ratio. The prescaler itself is not ...

  • Page 52

    ST62T55C ST62T65C/E65C 4.4 A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a typical conver- sion ...

  • Page 53

    A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect the sup- ply ...

  • Page 54

    ST62T55C ST62T65C/E65C 4.5 SERIAL PERIPHERAL INTERFACE (SPI) The SPI peripheral is an optimized synchronous serial interface with programmable transmission modes and master/slave capabilities supporting a wide range of industry standard SPI specifications. The SPI interface may also implement asynchro- nous ...

  • Page 55

    SERIAL PERIPHERAL INTERFACE SPI (Cont’d) 4.5.1 SPI Registers SPI Mode Control Register (MOD) Address: E2h — Read/Write Reset status: 00h 7 SPRUN SPIE CPHA SPCLK SPIN The MOD register defines and controls the trans- mission modes and characteristics. This register ...

  • Page 56

    ST62T55C ST62T65C/E65C SERIAL PERIPHERAL INTERFACE SPI (Cont’d) SPI DIV Register (DIV) Address: E1h — Read/Write Reset status: 00h 7 SPINT DOV6 DIV5 DIV4 DIV3 The SPIDIV register defines the transmission rate and frame format and contains the interrupt flag. Bits ...

  • Page 57

    SERIAL PERIPHERAL INTERFACE SPI (Cont’d) 4.6 SPI Timing Diagrams Figure 31. CPOL = 0 Clock Polarity Normal, CPHA = 0 Phase Selection Normal SPRUN SCK Sin Sampling Sout b7 Figure 32. CPOL = 1 Clock Polarity Inverted, CPHA = 0 ...

  • Page 58

    ST62T55C ST62T65C/E65C SERIAL PERIPHERAL INTERFACE SPI (Cont’d) Figure 33. CPOL = 0 Clock Polarity Normal, CPHA = 1 Phase Selection Shifted SPRUN SCK Sin Sampling Sout b7 Figure 34. CPOL = 1 Clock Polarity Inverted, CPHA = 1 Phase Selection ...

  • Page 59

    SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core ...

  • Page 60

    ST62T55C ST62T65C/E65C 5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, ...

  • Page 61

    INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either a data space ...

  • Page 62

    ST62T55C ST62T65C/E65C INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either ...

  • Page 63

    Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 2 JRNZ 4 ...

  • Page 64

    ST62T55C ST62T65C/E65C Opcode Map Summary (Continued) LOW 8 9 1000 1001 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr 2 ext 1 ...

  • Page 65

    ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the ...

  • Page 66

    ST62T55C ST62T65C/E65C 6.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A Operating Supply Voltage (Except ST626xB ROM devices Operating Supply Voltage (ST626xB ROM devices) 2) Oscillator Frequency (Except ST626xB ROM devices) f OSC 2) Oscillator Frequency (ST626xB ...

  • Page 67

    DC ELECTRICAL CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage V Hys All Input ...

  • Page 68

    ST62T55C ST62T65C/E65C DC ELECTRICAL CHARACTERISTICS (Cont’ -40 to +85°C unless otherwise specified)) A Symbol Parameter V LVD Threshold in power- LVD threshold in powerdown dn Low Level Output Voltage All Output pins V OL Low Level ...

  • Page 69

    A/D CONVERTER CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter Res Resolution (1) (2) A Total Accuracy TOT t Conversion Time C ZIR Zero Input Reading FSR Full Scale Reading Analog Input Current During AD ...

  • Page 70

    ST62T55C ST62T65C/E65C Figure 36. Vol versus Iol on all I/O port at Vdd= This curves represents typical variations and is given for guidance only Figure 37. Vol versus Iol on all I/O port ...

  • Page 71

    Figure 39. Vol versus Iol for High sink (30mA) I/O ports at Vdd= This curves represents typical variations and is given for guidance only Figure 40. Voh versus Ioh on all I/O ...

  • Page 72

    ST62T55C ST62T65C/E65C Figure 42. Idd WAIT versus V 2.5 2 1 This curves represents typical variations and is given for guidance only Figure 43. Idd STOP versus This ...

  • Page 73

    Figure 45. Idd WAIT versus V 2.5 2 1 This curves represents typical variations and is given for guidance only Figure 46. Idd RUN versus This curves represents typical ...

  • Page 74

    ST62T55C ST62T65C/E65C Figure 48. RC frequency versus This curves represents typical variations and is given for guidance only Figure 49. RC frequency versus 0.1 3 This curves represents typical variations and is given for ...

  • Page 75

    GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 50. 28-Pin Plastic Dual In-Line Package, 600-mil Width Figure 51. 28-Pin Plastic Small Outline Package, 300-mil Width ...

  • Page 76

    ST62T55C ST62T65C/E65C PACKAGE MECHANICAL DATA (Cont’d) Figure 5228-Ceramic Dual In Line Package, 600-mil Width Figure 53. 28-Pin Plastic Shrink Small Outline Package 76/86 CDIP28W inches Dim. Min Typ ...

  • Page 77

    ... Memory (Bytes) ST62E65CF1 3884 (EPROM) ST62T55CB6 ST62T55CB3 ST62T55CM6 3884 (OTP) ST62T55CM3 ST62T55CN6 ST62T55CN3 ST62T65CB6 ST62T65CB3 ST62T65CM6 3884 (OTP) ST62T65CM3 ST62T65CN6 ST62T65CN3 ST62T55C ST62T65C/E65C EEPROM (Bytes) Temperature Range 128 0 to +70°C - 85°C - 125°C - 85°C None - 125°C - 85°C - 125°C - 85°C - 125° ...

  • Page 78

    ST62T55C ST62T65C/E65C Notes: 78/86 ...

  • Page 79

    FASTROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table ...

  • Page 80

    ... MCU. The listing is then returned to the customer who must thoroughly check, com- plete, sign and return it to STMicroelectronics. The signed listing forms a part of the contractual agree- ment for the production of the specific customer MCU ...

  • Page 81

    SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage ...

  • Page 82

    ST6255C ST6265B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6255C and ST6265B are mask pro- grammed ROM version of ST62T55C and ST62T65C OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the ...

  • Page 83

    ... ST6265BN6/XXX ST6265BN3/XXX listing is then returned to the customer who must thoroughly check, complete, sign and return it to STMicroelectronics. The signed listing forms a part of the contractual agreement for the creation of the specific customer mask. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points ...

  • Page 84

    ... Enabled [ ] Enabled [ ] Enabled FASTROM Enabled ROM Enabled Fuse is blown by STMicroelectronics [ ] Fuse can be blown by the customer [ ] Disabled [ ] Enabled [ ] Enabled [ ] Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 85

    SUMMARY OF CHANGES Rev. Modification of “Additional Notes for EEPROM Parallel Mode” (p.13) In section 4.2.4 on page 45: vector #4 instead of vector #3 in description of bit 6 (TSCR register). 2.9 Changed f values in section 6.4 ...

  • Page 86

    ... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...