NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 620

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NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
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Note:
16.1.1
16.1.2
620
Internal reset as a result of D3
except the following BIOS programmed registers as BIOS may not be invoked following
the D3-to-D0 transition. All resume well registers will not be reset by the D3
transition.
Core well registers not reset by the D3
Resume well registers will not be reset by the D3
VID—Vendor Identification Register (Audio—D30:F2)
Offset:
Default Value:
Lockable:
DID—Device Identification Register (Audio—D30:F2)
Offset:
Default Value:
Lockable:
• offset 2Ch
• offset 2Eh
• offset 40h – Programmable Codec ID (PCID)
• offset 41h – Configuration (CFG)
• offset 54h
• Bus Mastering Register: Global Status Register, bits 17:16
• Bus Mastering Register: SDATA_IN MAP register, bits 7:3
15:0
15:0
Bit
Bit
Vendor ID. This is a 16-bit value assigned to Intel.
Device ID — RO. This is a 16-bit value assigned to the Intel
controller. Refer to the Intel
for the value of the Device ID Register.
2Fh – Subsystem ID (SID)
55h – Power Management Control and Status (PCS)
2Dh – Subsystem Vendor ID (SVID)
00h
8086h
No
02h
See bit description
No
01h
03h
AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
HOT
®
to D0 transition will reset all the core well registers
I/O Controller Hub 7 (ICH7) Family Specification Update
HOT
Description
Description
to D0 transition:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
HOT
to D0 transition:
Intel
®
RO
16 Bits
Core
RO
16 Bits
Core
ICH7 AC ‘97 Audio
®
ICH7 Family Datasheet
HOT
to D0

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