NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 668

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NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
Bit
5
VGA Palette Snoop (VPS) — Reserved per the PCI Express* Base Specification.
Postable Memory Write Enable (PMWE) — Reserved per the PCI Express* Base
4
Specification.
3
Special Cycle Enable (SCE) — Reserved per the PCI Express* Base Specification.
Bus Master Enable (BME) — R/W.
0 = Disable. All cycles from the device are master aborted
2
1 = Enable. Allows the root port to forward cycles onto the backbone from a PCI
Express* device.
Memory Space Enable (MSE) — R/W.
0 = Disable. Memory cycles within the range specified by the memory base and limit
1
registers are master aborted on the backbone.
1 = Enable. Allows memory cycles within the range specified by the memory base and
limit registers can be forwarded to the PCI Express device.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable. I/O cycles within the range specified by the I/O base and limit registers
0
are master aborted on the backbone.
1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit
registers can be forwarded to the PCI Express device.
18.1.4
PCISTS—PCI Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 06h
Default Value:
0010h
Bit
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
15
1 = Root port received a command or data from the backbone with a parity error. This
is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set.
Signaled System Error (SSE) — R/WC.
14
0 = No system error signaled.
1 = Root port signaled a system error to the internal SERR# logic.
Received Master Abort (RMA) — R/WC.
0 = Root port has not received a completion with unsupported request status from the
13
backbone.
1 = Root port received a completion with unsupported request status from the
backbone.
Received Target Abort (RTA) — R/WC.
12
0 = Root port has not received a completion with completer abort from the backbone.
1 = Root port received a completion with completer abort from the backbone.
Signaled Target Abort (STA) — R/WC.
0 = No target abort received.
11
1 = Root port forwarded a target abort received from the downstream device onto the
backbone.
DEVSEL# Timing Status (DEV_STS) — Reserved per the PCI Express* Base
10:9
Specification.
668
PCI Express* Configuration Registers (Desktop and Mobile Only)
Description
07h
Attribute:
Size:
Description
R/WC, RO
16 bits
®
Intel
ICH7 Family Datasheet

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