LPC2420_60

Manufacturer Part NumberLPC2420_60
DescriptionNXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
ManufacturerNXP Semiconductors
LPC2420_60 datasheet
 


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LPC2420/2460
Flashless 16-bit/32-bit microcontroller; Ethernet, CAN,
ISP/IAP, USB 2.0 device/host/OTG, external memory interface
Rev. 6.1 — 22 September 2011
1. General description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2420/2460 is flashless. The LPC2420/2460 can execute both
32-bit ARM and 16-bit Thumb instructions. Support for the two instruction sets means
engineers can choose to optimize their application for either performance or code size at
the sub-routine level. When the core executes instructions in Thumb state it can reduce
code size by more than 30 % with only a small loss in performance while executing
instructions in ARM state maximizes core performance.
The LPC2420/2460 microcontroller is ideal for multi-purpose communication applications.
It incorporates a 10/100 Ethernet Media Access Controller (MAC) (LPC2460 only), a USB
full-speed device/host/OTG controller with 4 kB of endpoint RAM, four UARTs, two
Controller Area Network (CAN) channels (LPC2460 only), an SPI interface, two
Synchronous Serial Ports (SSP), three I
this collection of serial communications interfaces are the following feature components;
an on-chip 4 MHz internal precision oscillator, 82/98 kB of total RAM consisting of 64 kB
of local SRAM, 16 kB SRAM for Ethernet (LPC2460 only), 16 kB SRAM for general
purpose DMA, 2 kB of battery powered SRAM, and an External Memory Controller
(EMC). These features make this device optimally suited for communication gateways
and protocol converters. Complementing the many serial communication controllers,
versatile clocking capabilities, and memory features are various 32-bit timers, an
improved 10-bit ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to
160 fast GPIO lines. The LPC2420/2460 connects 64 of the GPIO pins to the hardware
based Vector Interrupt Controller (VIC) that means these external inputs can generate
edge-triggered interrupts. All of these features make the LPC2420/2460 particularly
suitable for industrial control and medical systems.
2. Features and benefits
ARM7TDMI-S processor, running at up to 72 MHz.
82/98 kB on-chip SRAM includes:
64 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
(LPC2460 only)
16 kB SRAM for general purpose DMA use also accessible by the USB.
2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet
DMA, and USB DMA with no contention (LPC2460 only).
Product data sheet
2
2
C interfaces, and an I
S interface. Supporting

LPC2420_60 Summary of contents

  • Page 1

    ... ISP/IAP, USB 2.0 device/host/OTG, external memory interface Rev. 6.1 — 22 September 2011 1. General description NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded trace. The LPC2420/2460 is flashless. The LPC2420/2460 can execute both 32-bit ARM and 16-bit Thumb instructions ...

  • Page 2

    ... Ethernet wake-up interrupt (LPC2460 only), CAN bus activity (LPC2460 only)).  Two independent power domains allow fine tuning of power consumption based on needed features. LPC2420_60 Product data sheet 2 C-bus interfaces (one with open-drain and two with standard port pins (Inter-IC Sound) interface for digital audio input or output. It can be used with All information provided in this document is subject to legal disclaimers. Rev. 6.1 — ...

  • Page 3

    ... LPC2420FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15  15  0.7 mm SOT950-1 LPC2460FBD208 LQFP208 LPC2460FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15  15  0.7 mm SOT950-1 LPC2420_60 Product data sheet Description plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm plastic low profile quad flat package ...

  • Page 4

    ... Type number Flash (kB) LPC2420FBD208 N LPC2420FET208 N LPC2460FBD208 N LPC2460FET208 N LPC2420_60 Product data sheet SRAM (kB) External Ethernet bus Full 32-bit - 98 Full 32-bit MII/RMII 98 Full 32-bit MII/RMII 98 Full 32-bit MII/RMII All information provided in this document is subject to legal disclaimers. ...

  • Page 5

    ... D/A CONVERTER AOUT VBAT 2 kB BATTERY RAM power domain 2 RTCX1 RTC RTCX2 OSCILLATOR ALARM WATCHDOG TIMER SYSTEM CONTROL (1) LPC2460 only. Fig 1. LPC2420/2460 block diagram LPC2420_60 Product data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 64 kB TEST/DEBUG SRAM INTERFACE INTERNAL ARM7TDMI-S ...

  • Page 6

    ... Fig 2. LPC2420/2460 pinning LQFP208 package Fig 3. LPC2420/2460 pinning TFBGA208 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 P3[27]/D27/ 2 CAP1[0]/PWM1[4] 5 P1[4]/ENET_TX_EN 6 9 P1[17]/ENET_MDIO 10 13 P3[20]/D20/ 14 PWM0[5]/DSR1 LPC2420_60 Product data sheet 1 LPC2420FBD208 LPC2460FBD208 52 ball A1 index area ...

  • Page 7

    ... P2[4]/PWM1[5]/ DSR1/TRACESYNC Row E 1 P0[26]/AD0[3]/ 2 AOUT/RXD3 14 P2[1]/PWM1[2]/RXD1/ 15 PIPESTAT0 Row F 1 P0[25]/AD0[2]/ 2 I2SRX_SDA/TXD3 14 P4[11]/A11 15 Row G 1 P3[5]/ n.c. 15 LPC2420_60 Product data sheet …continued Pin Symbol - P3[10]/D10 SSIO P4[29]/BLS3/ 11 MAT2[1]/RXD3 P3[19]/D19/ 15 PWM0[4]/DCD1 - TDI 3 P3[22]/D22/ 7 PCAP0[0]/RI1 P3[21]/D21/ 11 PWM0[6]/DTR1 P0[9]/I2STX_SDA/ ...

  • Page 8

    ... P2[24]/CKEOUT0 6 9 P1[23]/USB_RX_DP1/ 10 PWM1[4]/MISO0 13 P2[15]/CS3/ 14 CAP2[1]/SCL1 17 V DD(3V3) Row R 1 P0[12]/USB_PPWR2/ 2 MISO1/AD0[6] 5 P3[24]/D24/ 6 CAP0[1]/PWM1[ SSIO LPC2420_60 Product data sheet …continued Pin Symbol P3[14]/D14 3 P2[8]/TD2/ 16 TXD2/TRACEPKT3 V 3 SSA P4[23]/A23/ 16 RXD2/MOSI1 RTCX1 3 P0[18]/DCD1/ 16 MOSI0/MOSI RTCX2 3 P4[26]/BLS0 16 3 RESET P4[21]/A21/ ...

  • Page 9

    ... CAP3[1]/SSEL0 9 P4[0]/ DD(3V3) 17 P4[16]/A16 6.2 Pin description Table 4. Pin description Symbol Pin P0[0] to P0[31] [1] P0[0]/RD1/ 94 TXD3/SDA1 [1] P0[1]/TD1/RXD3/ 96 SCL1 [1] P0[2]/TXD0 202 LPC2420_60 Product data sheet …continued Pin Symbol P0[11]/RXD2/SCL2/ 15 MAT3[1] - P0[31]/USB_D+2 3 P3[23]/D23/ 7 CAP0[0]/PCAP1[0] P1[25]/USB_LS1/ 11 USB_HSTEN1/MAT1[1] P0[1]/TD1/RXD3/SCL1 15 - P3[25]/D25/ 3 MAT0[0]/PWM1[2] P1[19]/USB_TX_E1/ 7 USB_PPWR1/CAP1[1] P4[1]/A1 11 ...

  • Page 10

    ... I2STX_CLK/ SCK1/MAT2[1] [1] P0[8]/ 160 I2STX_WS/ MISO1/MAT2[2] [1] P0[9]/ 158 I2STX_SDA/ MOSI1/MAT2[3] [1] P0[10]/TXD2/ 98 SDA2/MAT3[0] LPC2420_60 Product data sheet Ball Type Description [1] D6 I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. [1] B12 I/O P0[4] — General purpose digital input/output pin. I/O I2SRX_CLK — Receive Clock driven by the master and received by the slave ...

  • Page 11

    ... P0[15]/TXD1/ 128 SCK0/SCK [1] P0[16]/RXD1/ 130 SSEL0/SSEL [1] P0[17]/CTS1/ 126 MISO0/MISO [1] P0[18]/DCD1/ 124 MOSI0/MOSI LPC2420_60 Product data sheet Ball Type Description [1] R14 I/O P0[11] — General purpose digital input/output pin. I RXD2 — Receiver input for UART2. 2 I/O SCL2 — clock input/output (this is not an open-drain pin). ...

  • Page 12

    ... P0[24]/AD0[1]/ 16 I2SRX_WS/ CAP3[1] [2] P0[25]/AD0[2]/ 14 I2SRX_SDA/ TXD3 [2][3] P0[26]/AD0[3]/ 12 AOUT/RXD3 [4] P0[27]/SDA0 50 LPC2420_60 Product data sheet Ball Type Description [1] L17 I/O P0[19] — General purpose digital input/output pin. I DSR1 — Data Set Ready input for UART1. O MCICLK — Clock output line for SD/MMC interface. 2 I/O SDA1 — data input/output (this is not an open-drain pin) ...

  • Page 13

    ... PWM0[2] [1] P1[4]/ 192 ENET_TX_EN [1] P1[5]/ 156 ENET_TX_ER/ MCIPWR/ PWM0[3] [1] P1[6]/ 171 ENET_TX_CLK/ MCIDAT0/ PWM0[4] LPC2420_60 Product data sheet Ball Type Description [4] R3 I/O P0[28] — General purpose digital input/output pin. 2 I/O SCL0 — clock input/output. Open-drain output (for I compliance). [5] U4 I/O P0[29] — General purpose digital input/output pin. ...

  • Page 14

    ... ENET_RX_ER [1] P1[15]/ 182 ENET_REF_CLK/ ENET_RX_CLK [1] P1[16]/ 180 ENET_MDC [1] P1[17]/ 178 ENET_MDIO LPC2420_60 Product data sheet Ball Type Description [1] D14 I/O P1[7] — General purpose digital input/output pin. I ENET_COL — Ethernet Collision detect (MII interface) (LPC2460 only). I/O MCIDAT1 — Data line 1 for SD/MMC interface. O PWM0[5] — Pulse Width Modulator 0, output 5. ...

  • Page 15

    ... PWM1[4]/MISO0 [1] P1[24]/ 78 USB_RX_DM1/ PWM1[5]/MOSI0 [1] P1[25]/ 80 USB_LS1/ USB_HSTEN1/ MAT1[1] LPC2420_60 Product data sheet Ball Type Description [1] P7 I/O P1[18] — General purpose digital input/output pin. O USB_UP_LED1 — USB port 1 GoodLink LED indicator LOW when device is configured (non-control endpoints enabled), or when host is enabled and has detected a device on the bus HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend ...

  • Page 16

    ... TXD1/ TRACECLK [1] P2[1]/PWM1[2]/ 152 RXD1/ PIPESTAT0 [1] P2[2]/PWM1[3]/ 150 CTS1/ PIPESTAT1 LPC2420_60 Product data sheet Ball Type Description [1] R10 I/O P1[26] — General purpose digital input/output pin. O USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver). O PWM1[6] — Pulse Width Modulator 1, channel 6 output. ...

  • Page 17

    ... P2[9]/ 132 USB_CONNECT1/ RXD2/ EXTIN0 [6] P2[10]/EINT0 110 [6] P2[11]/EINT1/ 108 MCIDAT1/ I2STX_CLK LPC2420_60 Product data sheet Ball Type Description [1] E16 I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O PIPESTAT2 — Pipeline Status, bit 2. ...

  • Page 18

    ... P2[21]/DYCS1 81 [1] P2[22]/DYCS2/ 85 CAP3[0]/SCK0 [1] P2[23]/DYCS3/ 64 CAP3[1]/SSEL0 [1] P2[24]/ 53 CKEOUT0 LPC2420_60 Product data sheet Ball Type Description [6] N14 I/O P2[12] — General purpose digital input/output pin. I EINT2 — External interrupt 2 input. I/O MCIDAT2 — Data line 2 for SD/MMC interface. I/O I2STX_WS — Transmit Word Select driven by the master and received by the slave ...

  • Page 19

    ... P3[2]/D2 207 [1] P3[3]/D3 3 [1] P3[4]/D4 13 [1] P3[5]/D5 17 [1] P3[6]/D6 23 [1] P3[7]/D7 27 LPC2420_60 Product data sheet Ball Type Description [1] R4 I/O P2[25] — General purpose digital input/output pin. O CKEOUT1 — SDRAM clock enable 1. [1] T4 I/O P2[26] — General purpose digital input/output pin. O CKEOUT2 — SDRAM clock enable 2. O MAT3[0] — Match output for Timer 3, channel 0. ...

  • Page 20

    ... PWM0[2]/RXD1 [1] P3[18]/D18/ 151 PWM0[3]/CTS1 [1] P3[19]/D19/ 161 PWM0[4]/DCD1 [1] P3[20]/D20/ 167 PWM0[5]/DSR1 LPC2420_60 Product data sheet Ball Type Description [1] D8 I/O P3[8] — General purpose digital input/output pin. I/O D8 — External memory data line 8. [1] C5 I/O P3[9] — General purpose digital input/output pin. ...

  • Page 21

    ... P3[28]/D28/ 5 CAP1[1]/ PWM1[5] [1] P3[29]/D29/ 11 MAT1[0]/ PWM1[6] [1] P3[30]/D30/ 19 MAT1[1]/ RTS1 LPC2420_60 Product data sheet Ball Type Description [1] C10 I/O P3[21] — General purpose digital input/output pin. I/O D21 — External memory data line 21. O PWM0[6] — Pulse Width Modulator 0, output 6. O DTR1 — Data Terminal Ready output for UART1. ...

  • Page 22

    ... P4[12]/A12 149 [1] P4[13]/A13 155 [1] P4[14]/A14 159 [1] P4[15]/A15 173 [1] P4[16]/A16 101 LPC2420_60 Product data sheet Ball Type Description [1] J3 I/O P3[31] — General purpose digital input/output pin. I/O D31 — External memory data line 31. O MAT1[2] — Match output for Timer 1, channel 2. I/O Port 4: Port 32-bit I/O port with individual direction controls for each bit ...

  • Page 23

    ... P4[27]/BLS1 139 [1] P4[28]/BLS2/ 170 MAT2[0]/TXD3 [1] P4[29]/BLS3/ 176 MAT2[1]/RXD3 [1] P4[30]/CS0 187 LPC2420_60 Product data sheet Ball Type Description [1] P14 I/O P4[17] — General purpose digital input/output pin. I/O A17 — External memory address line 17. [1] P15 I/O P4[18] — General purpose digital input/output pin. ...

  • Page 24

    ... V 15, 60, DD(3V3) 71, 89, 112, 125, 146, 165, 181, [7] 198 n.c. 30, 117, [7] 141 LPC2420_60 Product data sheet Ball Type Description [1] A4 I/O P4[31] — General purpose digital input/output pin. O CS1 — LOW active Chip Select 1 signal. [ ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC alarm is generated ...

  • Page 25

    ... When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. [12] If the RTC is not used, these pins can be left floating. LPC2420_60 Product data sheet Ball ...

  • Page 26

    ... The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: • the standard 32-bit ARM set • a 16-bit Thumb set LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © ...

  • Page 27

    ... FFFF 0x4000 0000 to 0x7FFF FFFF 0x8000 0000 to 0xDFFF FFFF 0xE000 0000 to 0xEFFF FFFF 0xF000 0000 to 0xFFFF FFFF LPC2420_60 Product data sheet and Figure 4. Section 7.25.6). LPC2420/2460 memory usage and details Address range details and description fast I/O 0x3FFF C000 to 0x3FFF FFFF ...

  • Page 28

    ... FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ LPC2420_60 Product data sheet 4.0 GB ...

  • Page 29

    ... SDRAM memory support. • Static memory features include: LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © ...

  • Page 30

    ... AHB slave DMA programming interface. The GPDMA is programmed by writing to the DMA control registers over the AHB slave interface. LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 LPC2420/2460 ...

  • Page 31

    ... All I/O default to inputs after reset. • Backward compatibility with other earlier devices is maintained with legacy port 0 and port 1 registers appearing at the original addresses on the APB. LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 ...

  • Page 32

    ... Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 ...

  • Page 33

    ... The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies with the OHCI specification. LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. ...

  • Page 34

    ... Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © ...

  • Page 35

    ... Receiver FIFO trigger points and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. LPC2420_60 Product data sheet i(VREF) . i(VREF) All information provided in this document is subject to legal disclaimers. ...

  • Page 36

    ... SD/MMC card interface The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Specification Version 2.11. LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 ...

  • Page 37

    ... The I 2 7.19 I S-bus serial I/O controllers 2 The I S-bus provides a standard communication interface for digital audio applications. LPC2420_60 Product data sheet 2 C-bus controllers compliant bus interface with open-drain pins use standard I/O pins and do not support powering off of individual 2 C-bus can be used for test and diagnostic purposes ...

  • Page 38

    ... Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. LPC2420_60 Product data sheet 2 S connection has one master, which is always the 2 S interface on the LPC2420/2460 provides a separate All information provided in this document is subject to legal disclaimers. Rev. 6.1 — ...

  • Page 39

    ... LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 ...

  • Page 40

    ... LPC2420/2460, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock. Also, the RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V supply used by the rest of the device. LPC2420_60 Product data sheet  256  cy(WDCLK)  ...

  • Page 41

    ... CPU operating frequency, by the PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. ...

  • Page 42

    ... V characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. LPC2420_60 Product data sheet Section 7.24.2 for additional information. ramp (in the case of power on), the type of crystal and its electrical DD(3V3) All information provided in this document is subject to legal disclaimers ...

  • Page 43

    ... SRAM. The customers need to reconfigure the PLL and clock dividers accordingly after a wake-up from Power-down mode. LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 ...

  • Page 44

    ... When the CPU and the rest of chip functions are stopped and power removed, the RTC can supply an alarm output that may be used by external hardware to restore chip power and resume operation. LPC2420_60 Product data sheet pins power the on-chip DC-to-DC converter which in turn provides power to and V pins together ...

  • Page 45

    ... V, at which point the power-on reset circuitry maintains the overall Reset. Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95 V detection to reliably interrupt regularly-executed event loop to sense the condition. LPC2420_60 Product data sheet Table 5 “LPC2420/2460 memory usage and Section 14.1 “Suggested boot memory interface solutions” ...

  • Page 46

    ... The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. LPC2420_60 Product data sheet All information provided in this document is subject to legal disclaimers. ...

  • Page 47

    ... lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2420/2460 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory. LPC2420_60 Product data sheet 1 ⁄ ...

  • Page 48

    ... The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC2420_60 Product data sheet [1] Conditions ...

  • Page 49

    ... JEDEC (4.5 in  4 in) 0 m/s 27.4 1 m/s 25.7 2.5 m/s 24.4 Single-layer (4.5 in  3 in) 0 m/s 35.4 1 m/s 31.2 2.5 m/s 29.2 jc 8.8 jb 15.4 LPC2420_60 Product data sheet      – = ambient temperature (C), = the package junction-to-ambient thermal resistance (C/W) = sum of internal and I/O power dissipation   +85 C unless otherwise specified ...

  • Page 50

    ... I OFF-state output OZ current I I/O latch-up current latch V input voltage I V output voltage O V HIGH-level input IH voltage LPC2420_60 Product data sheet Conditions [ 3.3 V; DD(DCDC)(3V3 C; code T amb while(1){} executed from the on-chip SRAM; no peripherals enabled; PCLK = CCLK / 8 CCLK = 12 MHz CCLK = 72 MHz [3] ...

  • Page 51

    ... LI Oscillator pins V input voltage on pin i(XTAL1) XTAL1 V output voltage on pin o(XTAL2) XTAL2 V input voltage on pin i(RTCX1) RTCX1 V output voltage on pin o(RTCX2) RTCX2 LPC2420_60 Product data sheet …continued Conditions =    0 DD(3V3 0 ...

  • Page 52

    ... Allowed as long as the current limit does not exceed the maximum current allowed by the device. [11] Minimum condition for V = 4.5 V, maximum condition for V I [12 SSIO SSCORE [13] Includes external resistors of 33   and D. LPC2420_60 Product data sheet …continued Conditions 0 V < V < 3 (D+)  (D) includes V range ...

  • Page 53

    ... NXP Semiconductors 10.1 Power-down mode I DD(IO) (μA) Fig 5. I (μA) Fig 6. LPC2420_60 Product data sheet −2 −4 −40 − 3 i(VBAT) DD(DCDC)(3V3) amb I/O maximum supply current I 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) ...

  • Page 54

    ... NXP Semiconductors I DD(DCDC)pd(3v3) Fig 7. 10.2 Deep power-down mode I DD(IO) (μA) Fig 8. LPC2420_60 Product data sheet 800 (μA) 600 400 V = 3.3 V DD(DCDC)(3V3) 200 V = 3.0 V DD(DCDC)(3V3) 0 −40 −  3 DD(3V3) i(VBAT) amb Total DC-to-DC converter supply current I in Power-down mode ...

  • Page 55

    ... NXP Semiconductors I (μA) Fig 9. I DD(DCDC)dpd(3v3) Fig 10. Total DC-to-DC converter maximum supply current I LPC2420_60 Product data sheet 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I power-down mode 100 (μ 3.3 V DD(DCDC)(3V3) ...

  • Page 56

    ... NXP Semiconductors 10.3 Electrical pin characteristics V Fig 11. Typical HIGH-level output voltage V (mA) Fig 12. Typical LOW-level output current I LPC2420_60 Product data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2.4 2 Conditions 3.3 V; standard port pins. DD(3V3 0.2 Conditions 3.3 V; standard port pins. ...

  • Page 57

    ... Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] [3] Bus capacitance C in pF, from 400 pF. b Fig 13. External clock timing (with an amplitude of at least V LPC2420_60 Product data sheet over specified ranges. DD(3V3) Conditions ...

  • Page 58

    ... JR1 t receiver jitter for paired transitions JR2 t EOP width at receiver EOPR1 t EOP width at receiver EOPR2 [1] Characterized but not implemented as production test. Guaranteed by design. LPC2420_60 Product data sheet  3.6 V. [1] DD(3V3) Conditions - - [1] over specified ranges. Conditions pin configured as output pin configured as output ,unless otherwise specified ...

  • Page 59

    Static external memory interface Table 14. Dynamic characteristics: Static external memory interface    pF amb DD(DCDC)(3V3) Symbol Parameter Conditions [1] Common to read and write ...

  • Page 60

    Table 14. Dynamic characteristics: Static external memory interface    pF amb DD(DCDC)(3V3) Symbol Parameter Conditions t WE HIGH to data invalid WEHDNV time t BLS HIGH ...

  • Page 61

    ... See Figure 18. LPC2420_60 Product data sheet = 3.6 V, EMC Dynamic Read Config Register = 0x0 DD(DCDC)(3V3) DD(3V3) Conditions All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 LPC2420/2460 Flashless 16-bit/32-bit microcontroller ...

  • Page 62

    ... Write cycle parameters t data output valid delay d(QV) time t data output hold time h(Q) [1] See Figure 18. LPC2420_60 Product data sheet 3.3 V, EMC Dynamic Read Config Register = 0x1 (RD = 01), DD(DCDC)(3V3) DD(3V3) Conditions Min [1] -  [1] [1] -  [1] ...

  • Page 63

    ... NXP Semiconductors 11.6 Timing CS addr data t CSLOEL OE BLS Fig 14. External memory read access CS BLS/WE addr data OE Fig 15. External memory write access LPC2420_60 Product data sheet t CSLAV OELAV t OELOEH t BLSLAV t CSLAV t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV All information provided in this document is subject to legal disclaimers. ...

  • Page 64

    ... Fig 16. Differential data-to-EOP transition skew and EOP width shifting edges SCK MOSI MISO Fig 17. MISO line set-up time in SSP Master mode Fig 18. Signal timing LPC2420_60 Product data sheet crossover point crossover point differential data to SE0/EOP skew n × PERIOD ...

  • Page 65

    ... T ADC and the ideal transfer curve. See [8] See Figure 20. LPC2420_60 Product data sheet   +85 C unless otherwise specified; ADC frequency 4.5 MHz. Conditions ) is the difference between the actual step width and the ideal step width. See ...

  • Page 66

    ... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 19. ADC characteristics LPC2420_60 Product data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ...

  • Page 67

    ... NXP Semiconductors AD0[y] Fig 20. Suggested ADC interface - LPC2420/2460 AD0[y] pin LPC2420_60 Product data sheet LPC2XXX 20 kΩ SAMPLE SSIO, SSCORE All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 LPC2420/2460 Flashless 16-bit/32-bit microcontroller R vsi ...

  • Page 68

    ... CS1 OE BLS1 D[15:8] A[a_b:1] Fig 21. Booting from two 8-bit memory chips Fig 22. Booting from a single 16-bit memory chip LPC2420_60 Product data sheet   +85 C unless otherwise specified Conditions CE ...

  • Page 69

    ... NXP Semiconductors 14.2 Suggested USB interface solutions LPC24XX Fig 23. LPC2420/2460 USB interface on a self-powered device LPC24XX Fig 24. LPC2420/2460 USB interface on a bus-powered device LPC2420_60 Product data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1.5 kΩ V BUS Ω USB_D Ω USB_D− ...

  • Page 70

    ... USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 25. LPC2420/2460 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2420_60 Product data sheet RESET_N ADR/PSW OE_N/INT_N V DD SPEED ...

  • Page 71

    ... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 26. LPC2420/2460 USB OTG port configuration: VP_VM mode LPC2420_60 Product data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1302 ADR/PSW SPEED SUSPEND SCL SDA INT_N ...

  • Page 72

    ... USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 V BUS Fig 27. LPC2420/2460 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2420_60 Product data sheet Ω 33 Ω 15 kΩ 15 kΩ ENA 5 V LM3526 ...

  • Page 73

    ... C = 100 pF. To limit the input voltage to the specified range, choose an additional i capacitor to ground C slave mode, a minimum of 200 mV (RMS) is needed. Fig 29. Slave mode operation of the on-chip oscillator LPC2420_60 Product data sheet Ω 33 Ω 15 kΩ ...

  • Page 74

    ... Table 19. Fundamental oscillation frequency F 1 MHz to 5 MHz 5 MHz to 10 MHz 10 MHz to 15 MHz 15 MHz to 20 MHz LPC2420_60 Product data sheet 29), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This and Table 20. Since the feedback resistance is integrated on chip, only a crystal and C ...

  • Page 75

    ... C from PCB and package are not taken into account. Table 21. Crystal load capacitance LPC2420_60 Product data sheet Recommended values for C X1 components parameters): high frequency mode Crystal load capacitance C OSC 10 pF ...

  • Page 76

    ... Fig 32. Standard I/O pin configuration with analog input LPC2420_60 Product data sheet shows the possible pin modes for standard I/O pins with analog input function: output enable output driver pull-down enable ...

  • Page 77

    ... NXP Semiconductors 14.7 Reset pin configuration Fig 33. Reset pin configuration LPC2420_60 Product data sheet reset GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 LPC2420/2460 Flashless 16-bit/32-bit microcontroller ESD ESD V SS 002aaf274 © ...

  • Page 78

    ... UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT459-1 136E30 Fig 34. Package outline SOT459-1 (LQFP208) LPC2420_60 Product data sheet X 105 104 ...

  • Page 79

    ... index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 mm 1.2 0.3 0.6 0.4 OUTLINE VERSION IEC SOT950-1 Fig 35. Package outline SOT950-1 (TFBGA208) LPC2420_60 Product data sheet ∅ ∅ scale D ...

  • Page 80

    ... POR PWM RMII SD/MMC SE0 SPI SSI SSP TTL UART USB LPC2420_60 Product data sheet Acronym list Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel ...

  • Page 81

    ... All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 LPC2420/2460 Flashless 16-bit/32-bit microcontroller Change notice Supersedes - LPC2420_60 v.6 interface”: Removed text "EMC - LPC2420_60 v.5 for DBGEN, TMS, TDI, TRST, and RTCK for TCK and TDO pins. for XTAL1 and XTAL2 pins. ...

  • Page 82

    ... Preliminary data sheet Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 22 September 2011 LPC2420/2460 Flashless 16-bit/32-bit microcontroller Change notice Supersedes , I , and I DD(DCDC)dpd(3V3) BATact - LPC2420_60 v.3 . DD(DCDC)act(3V3 DD(3V3) DD(DCDC)(3V3) - LPC2460 v.2 - LPC2460 v © NXP B.V. 2011. All rights reserved. ...

  • Page 83

    ... This document supersedes and replaces all information supplied prior to the publication hereof. LPC2420_60 Product data sheet [3] Definition This document contains data from the objective specification for product development. ...

  • Page 84

    ... Contact information For more information, please visit: For sales office addresses, please send an email to: LPC2420_60 Product data sheet whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s ...

  • Page 85

    ... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.14 UARTs 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.15 SPI serial I/O controller 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.16 SSP serial I/O controller . . . . . . . . . . . . . . . . . 36 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.17 SD/MMC card interface . . . . . . . . . . . . . . . . . 36 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2 7.18 I C-bus serial I/O controller . . . . . . . . . . . . . . 37 LPC2420_60 Product data sheet 7.18.1 Features 7.19 I 7.19.1 Features 7.20 General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 38 7.20.1 Features 7.21 Pulse width modulator . . . . . . . . . . . . . . . . . . 39 7.21.1 Features 7.22 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 40 7.22.1 Features 7.23 RTC and battery RAM . . . . . . . . . . . . . . . . . . 40 7 ...

  • Page 86

    ... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 22 September 2011 Document identifier: LPC2420_60 ...