LPC2420_60 NXP Semiconductors, LPC2420_60 Datasheet - Page 24

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LPC2420_60

Manufacturer Part Number
LPC2420_60
Description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
Table 4.
LPC2420_60
Product data sheet
Symbol
P4[31]/CS1
ALARM
USB_D2
DBGEN
TDO
TDI
TMS
TRST
TCK
RTCK
RSTOUT
RESET
XTAL1
XTAL2
RTCX1
RTCX2
V
V
V
V
n.c.
SSIO
SSCORE
SSA
DD(3V3)
Pin description
Pin
193
37
52
9
2
4
6
8
10
206
29
35
44
46
34
36
33, 63,
77, 93,
114,
133, 148,
169, 189,
200
32, 84,
172
22
15, 60,
71, 89,
112,
125, 146,
165,
181,
198
30, 117,
141
[1][8]
[1][9]
[1][8]
[1][8]
[1][8]
[7]
[1][9]
[10]
[7][11]
[7][11]
[7][12]
[7][12]
[7]
[1]
[1][8]
[7]
[7]
[7]
[7]
…continued
Ball
A4
N1
U1
F4
D3
C2
E3
D1
E2
C3
K3
M2
M4
N4
K2
L2
L3, T5,
R9,
P12,
N16,
H14,
E15, A12,
B6, A2
K4, P10,
D12
J2
G3,
P6, P8,
U13,
P17,
K16,
C17,
B13,
C9,
D7
J4, L14,
G14
[7]
[7][12]
[1][8]
[1]
[1][8]
[1][9]
[7][12]
[7]
[1][9]
[1][8]
[1][8]
[1][8]
[7][11]
[7]
[10]
[7][11]
[7]
[7]
[7]
All information provided in this document is subject to legal disclaimers.
Type
I/O
O
O
I/O
I
O
I
I
I
I
I/O
O
I
I
O
I
O
I
I
I
I
I
Rev. 6.1 — 22 September 2011
Description
P4[31] — General purpose digital input/output pin.
CS1 — LOW active Chip Select 1 signal.
ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH
when a RTC alarm is generated.
USB_D2 — USB port 2 bidirectional D line.
DBGEN — JTAG interface control signal. Also used for boundary
scanning.
TDO — Test data out for JTAG interface.
TDI — Test data in for JTAG interface.
TMS — Test Mode Select for JTAG interface.
TRST — Test Reset for JTAG interface.
TCK — Test Clock for JTAG interface. This clock must be slower than
1
RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins
(P2[9:0]) to operate as Trace port after reset.
RSTOUT — This is a 3.3 V pin. LOW on this pin indicates
LPC2420/2460 being in Reset state.
external reset input: A LOW on this pin resets the device, causing
I/O ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
ground: 0 V reference for the digital I/O pins.
ground: 0 V reference for the core.
analog ground: 0 V reference. This should nominally be the same
voltage as V
and error.
3.3 V supply voltage: This is the power supply voltage for the I/O
ports.
not connected pins: These pins must be left unconnected (floating).
6
of the CPU clock (CCLK) for the JTAG interface to operate.
SSIO
/V
SSCORE
Flashless 16-bit/32-bit microcontroller
, but should be isolated to minimize noise
LPC2420/2460
© NXP B.V. 2011. All rights reserved.
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