LPC2468

Manufacturer Part NumberLPC2468
DescriptionNXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
ManufacturerNXP Semiconductors
LPC2468 datasheet
 
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LPC2468
Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN,
ISP/IAP, USB 2.0 device/host/OTG, external memory interface
Rev. 6.1 — 6 September 2011
1. General description
NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2468 has 512 kB of on-chip high-speed flash memory. This
flash memory includes a special 128-bit wide memory interface and accelerator
architecture that enables the CPU to execute sequential instructions from flash memory at
the maximum 72 MHz system clock rate. This feature is available only on the LPC2000
ARM microcontroller family of products. The LPC2468 can execute both 32-bit ARM and
16-bit Thumb instructions. Support for the two instruction sets means engineers can
choose to optimize their application for either performance or code size at the sub-routine
level. When the core executes instructions in Thumb state it can reduce code size by
more than 30 % with only a small loss in performance while executing instructions in ARM
state maximizes core performance.
The LPC2468 microcontroller is ideal for multi-purpose communication applications. It
incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed
Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area
Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I
interfaces, and an I
interfaces are the following feature components; an on-chip 4 MHz internal precision
oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for
Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an
External Memory Controller (EMC). These features make this device optimally suited for
communication gateways and protocol converters. Complementing the many serial
communication controllers, versatile clocking capabilities, and memory features are
various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external
interrupt pins, and up to 160 fast GPIO lines. The LPC2468 connects 64 of the GPIO pins
to the hardware based Vector Interrupt Controller (VIC) that means these external inputs
can generate edge-triggered interrupts. All of these features make the LPC2468
particularly suitable for industrial control and medical systems.
2. Features and benefits
ARM7TDMI-S processor, running at up to 72 MHz.
512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
98 kB on-chip SRAM includes:
64 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
2
S interface. Supporting this collection of serial communications
Product data sheet
2
C

LPC2468 Summary of contents

  • Page 1

    ... ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 160 fast GPIO lines. The LPC2468 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC) that means these external inputs can generate edge-triggered interrupts ...

  • Page 2

    ... C-bus interfaces (one with open-drain and two with standard port pins (Inter-IC Sound) interface for digital audio input or output. It can be used with All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 3

    ... Type number Package Name Description plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm LPC2468FBD208 LQFP208 LPC2468FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15  15  0.7 mm SOT950-1 4.1 Ordering options Table 2. Ordering options Type number Flash ...

  • Page 4

    ... AD0 A/D CONVERTER D/A CONVERTER AOUT VBAT 2 kB BATTERY RAM power domain 2 RTCX1 RTC RTCX2 OSCILLATOR ALARM WATCHDOG TIMER SYSTEM CONTROL Fig 1. LPC2468 block diagram LPC2468 Product data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 64 kB 512 kB TEST/DEBUG SRAM FLASH INTERFACE ...

  • Page 5

    ... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC2468 pinning LQFP208 package Fig 3. LPC2468 pinning TFBGA208 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 P3[27]/D27/ 2 CAP1[0]/PWM1[4] 5 P1[4]/ENET_TX_EN 6 9 P1[17]/ENET_MDIO 10 13 P3[20]/D20/ 14 PWM0[5]/DSR1 LPC2468 Product data sheet 1 LPC2468FBD208 52 ball A1 ...

  • Page 6

    ... PWM0[3]/CTS1 - - TDO 4 P3[12]/D12 V 8 P3[8]/D8 DD(3V3 DD(DCDC)(3V3) SSCORE P2[2]/PWM1[3]/ 16 P1[13]/ENET_RX_DV CTS1/PIPESTAT1 - - TMS 4 P3[3]/D3 P2[3]/PWM1[4]/ 17 P2[6]/PCAP1[0]/ DCD1/PIPESTAT2 RI1/TRACEPKT1 P3[29]/D29/ 4 DBGEN MAT1[0]/PWM1[6] P2[5]/PWM1[6]/ 17 P3[16]/D16/ DTR1/TRACEPKT0 PWM0[1]/TXD1 DD(3V3) DDA P2[7]/RD2/ 17 P4[10]/A10 RTS1/TRACEPKT2 LPC2468 © NXP B.V. 2011. All rights reserved ...

  • Page 7

    ... MCIPWR/RD1 MCICMD/SCL1 P2[29]/DQMOUT1 4 XTAL2 V 17 P0[22]/RTS1/ SSIO MCIDAT0/TD1 P2[27]/CKEOUT3/ 4 P2[28]/DQMOUT0 MAT3[1]/MOSI0 P1[18]/USB_UP_LED1 DD(3V3) PWM1[1]/CAP1[ DD(DCDC)(3V3) SSIO P4[18]/A18 16 P4[19]/A19 - - P0[28]/SCL0 4 P2[25]/CKEOUT1 P2[19]/CLKOUT1 8 P1[21]/USB_TX_DM1/ PWM1[3]/SSEL0 P2[16]/CAS 12 P2[14]/CS2/ CAP2[0]/SDA1 LPC2468 © NXP B.V. 2011. All rights reserved ...

  • Page 8

    ... Single-chip 16-bit/32-bit micro Pin Symbol P4[4]/A4 16 P4[5]/ P3[26]/D26/ 4 P2[26]/CKEOUT2/ MAT0[1]/PWM1[3] MAT3[0]/MISO0 P0[14]/USB_HSTEN2/ 8 P2[20]/DYCS0 USB_CONNECT2/ SSEL1 P4[2]/A2 12 P1[27]/USB_INT1/ USB_OVRCR1/CAP0[1] P0[10]/TXD2/SDA2/ 16 P2[13]/EINT3/ MAT3[0] MCIDAT3/I2STX_SDA - - P2[18]/CLKOUT0 4 P0[29]/USB_D+1 P1[20]/USB_TX_DP1/ 8 P1[22]/USB_RCV1/ PWM1[2]/SCK0 USB_PWRD1/MAT1[0] P2[21]/DYCS1 12 P2[22]/DYCS2/ CAP3[0]/SCK0 P0[0]/RD1/TXD3/SDA1 16 P4[3]/ LPC2468 © NXP B.V. 2011. All rights reserved ...

  • Page 9

    ... RXD2 — Receiver input for UART2. 2 I/O SCL2 — clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro 2 S-bus specification. 2 S-bus 2 S-bus specification. 2 S-bus specification ...

  • Page 10

    ... DTR1 — Data Terminal Ready output for UART1. I/O MCICMD — Command line for SD/MMC interface. 2 I/O SCL1 — clock input/output (this is not an open-drain pin). All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 11

    ... Port 1: Port bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the Pin Connect block. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro 2 S-bus specification. 2 ...

  • Page 12

    ... ENET_RXD3 — Ethernet Receive Data (MII interface). I/O MCIDAT3 — Data line 3 for SD/MMC interface. I PCAP0[0] — Capture input for PWM0, channel 0. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 13

    ... USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver). O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 14

    ... O TXD1 — Transmitter output for UART1. O TRACECLK — Trace Clock. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro 2 C serial clock (OTG transceiver serial data (OTG transceiver). © NXP B.V. 2011. All rights reserved. ...

  • Page 15

    ... Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over control of the part after a reset. I EINT0 — External interrupt 0 input. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 16

    ... DYCS2 — SDRAM chip select 2. I CAP3[0] — Capture input for Timer 3, channel 0. I/O SCK0 — Serial clock for SSP0. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro 2 S-bus specification. 2 S-bus 2 S-bus specification. ...

  • Page 17

    ... D3 — External memory data line 3. [1] I/O P3[4] — General purpose digital input/output pin. I/O D4 — External memory data line 4. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 18

    ... D19 — External memory data line 19. O PWM0[4] — Pulse Width Modulator 0, output 4. I DCD1 — Data Carrier Detect input for UART1. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 19

    ... D29 — External memory data line 29. O MAT1[0] — Match output for Timer 1, channel 0. O PWM1[6] — Pulse Width Modulator 1, output 6. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 20

    ... A13 — External memory address line 13. [1] I/O P4[14] — General purpose digital input/output pin. I/O A14 — External memory address line 14. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 21

    ... BLS2 — LOW active Byte Lane select signal 2. O MAT2[0] — Match output for Timer 2, channel 0. O TXD3 — Transmitter output for UART3. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 22

    ... RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. [1] O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2468 being in Reset state. [10] I external reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...

  • Page 23

    ... C-bus 400 kHz specification. It requires an external pull-up to provide output 2 C-bus is floating and does not disturb the I All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro but should be isolated to minimize noise and error. 2 DD(3V3) C lines. Open-drain © ...

  • Page 24

    ... AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order. The LPC2468 implements two AHBs in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. ...

  • Page 25

    ... The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at speeds of 72 MHz. 7.3 On-chip SRAM The LPC2468 includes a SRAM memory reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. ...

  • Page 26

    ... FFFF 0xF000 0000 to 0xFFFF FFFF LPC2468 Product data sheet LPC2468 memory usage and details Address range details and description off-chip Memory four static memory banks each 0x8000 0000 - 0x80FF FFFF 0x8100 0000 - 0x81FF FFFF 0x8200 0000 - 0x82FF FFFF ...

  • Page 27

    ... FLASH REMAPPED FROM ON-CHIP FLASH) RESERVED ADDRESS SPACE ON-CHIP STATIC RAM 1.0 GB SPECIAL REGISTERS RESERVED ADDRESS SPACE ON-CHIP NON-VOLATILE MEMORY 0.0 GB LPC2468 memory map All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro 0xFFFF FFFF 0xF000 0000 0xE000 0000 ...

  • Page 28

    ... External memory controller The LPC2468 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals ...

  • Page 29

    ... Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.8 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2468 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions ...

  • Page 30

    ... The value of the output register may be read back as well as the current state of the port pins. LPC2468 use accelerated GPIO functions: • GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved. • ...

  • Page 31

    ... The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2468 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory via the EMC, as well as the SRAM located on another AHB ...

  • Page 32

    ... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, LPC2468 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with the DMA RAM all non-control endpoints. ...

  • Page 33

    ... Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. LPC2468 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro interface © NXP B.V. 2011. All rights reserved. ...

  • Page 34

    ... Optional conversion on transition of input pin or Timer Match signal • Individual result registers for each ADC channel to reduce interrupt overhead 7.14 10-bit DAC The DAC allows the LPC2468 to generate a variable analog output. The maximum output value of the DAC is V 7.14.1 Features • 10-bit DAC • ...

  • Page 35

    ... UART3 includes an IrDA mode to support infrared communication. 7.16 SPI serial I/O controller The LPC2468 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master ...

  • Page 36

    ... The I be controlled by more than one bus master connected to it. 2 The I C-bus implemented in LPC2468 supports bit rates up to 400 kbit/s (Fast I 7.19.1 Features • standard I • ...

  • Page 37

    ... Controls include reset, stop and mute options separately for I 7.21 General purpose 32-bit timers/external event counters The LPC2468 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers ...

  • Page 38

    ... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2468. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...

  • Page 39

    ... The RTC is a set of counters for measuring time when system power is on, and optionally when power is off. It uses little power in Power-down and Deep power-down modes. On the LPC2468, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock. The RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3 ...

  • Page 40

    ... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy. Upon power-up or any chip reset, the LPC2468 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.25.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL ...

  • Page 41

    ... PLL to lock, then connect to the PLL as a clock source. 7.25.3 Wake-up timer The LPC2468 begins operation at power-up and when awakened from Power-down and Deep power-down modes by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...

  • Page 42

    ... NXP Semiconductors 7.25.4 Power control The LPC2468 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements ...

  • Page 43

    ... If power is supplied to the LPC2468 during Deep power-down mode, wake-up can be caused by the RTC Alarm interrupt or by external Reset. While in Deep power-down mode, external device power may be removed. In this case, the LPC2468 will start up when external power is restored ...

  • Page 44

    ... Code security (Code Read Protection - CRP) This feature of the LPC2468 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. ...

  • Page 45

    ... If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.26.4 AHB The LPC2468 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB SRAM ...

  • Page 46

    ... The JTAG clock (TCK) must be slower than interface to operate. 7.27.2 Embedded trace Since the LPC2468 have significant amounts of on-chip memories not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port ...

  • Page 47

    ... All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro Min Max Unit 3.0 3.6 V 3.0 3.6 V 0.5 +4 ...

  • Page 48

    ... JEDEC (4.5 in  4 in) 0 m/s 1 m/s 2.5 m/s 8-layer (4.5 in  3 in) 0 m/s 1 m/s 2.5 m/s jc jb All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro (C), can be calculated using the following j and V . The I/O power dissipation Min Typ Max - ...

  • Page 49

    ... CCLK = 10 MHz CCLK = 72 MHz all peripherals enabled; PCLK = CCLK CCLK = 10 MHz CCLK = 72 MHz [ 3.3 V; DD(DCDC)(3V3 C T amb [3] [4] [3] Deep power-down mode All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro [1] Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 2.0 3.3 3.6 2.5 3 ...

  • Page 50

    ... V - DD(3V3) 0.4 [ 4 [ [10 [10 [11 15 50 [11 0.7V - DD(3V3 0.05V DD(3V3) [ [12 LPC2468 Max Unit A 3 A 3 A 3 100 mA 5 DD(3V3 0 0  A 150 85 A  0.3V V DD(3V3 0.4 V A 4  ...

  • Page 51

    ... GND with 33  series resistor; steady state drive drops below 1  i(VBAT) amb is grounded. DD(3V3 All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro [1] Min Typ Max 0.5 1.8 1.95 0.5 1.8 1.95 0.5 1.8 1.95  ...

  • Page 52

    ... All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 Single-chip 16-bit/32-bit micro V = 3.3 V DD(3V3 3.0 V DD(3V3 temperature (° C. versus temperature in Power-down mode DD(IO temperature (° C. amb versus temperature in Power-down BAT LPC2468 002aae049 85 002aae050 85 © NXP B.V. 2011. All rights reserved ...

  • Page 53

    ... 3 DD(3V3) DD(DCDC)(3V3) amb I/O maximum supply current I DD(IO) mode All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro 002aae051 35 60 temperature (°C) at different temperatures DD(DCDC)pd(3V3) 002aae046 35 60 temperature (° C. ...

  • Page 54

    ... Deep power-down mode All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 Single-chip 16-bit/32-bit micro temperature (° C amb versus temperature in Deep BAT temperature (°C) DD(DCDC)dpd(3V3) LPC2468 002aae047 85 002aae048 85 versus © NXP B.V. 2011. All rights reserved ...

  • Page 55

    ... 0.2 Conditions 3.3 V; standard port pins. DD(3V3) All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro 002aaf112 16 I (mA) OH versus HIGH-level output source current OH 002aaf111 °C 25 °C −40 °C 0.4 ...

  • Page 56

    ... SPI Master mode; see Figure CHCL CLCX CLCH T cy(clk) = 200 mV) i(RMS) All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro [1] [2] Min Typ Max 1000  0 cy(clk)  0.4 ...

  • Page 57

    ... Figure 16 see Figure must reject as EOP; see Figure 16 must accept as EOP; see Figure 16 All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro [2] Min Typ Max 3.96 4.02 4.04 - 32.768 - Min Typ Max 3 ...

  • Page 58

    ... V to 3.6 V; all voltages are measured with respect to DD(3V3) Conditions [1] [2] powered; < 100 cycles unpowered; < 100 cycles sector or multiple consecutive sectors [2] All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro Min Typ Max 10000 100000 - ...

  • Page 59

    Static external memory interface Table 15. Dynamic characteristics: Static external memory interface    pF amb DD(DCDC)(3V3) Symbol Parameter Conditions [1] Common to read and write ...

  • Page 60

    Table 15. Dynamic characteristics: Static external memory interface    pF amb DD(DCDC)(3V3) Symbol Parameter Conditions t WE HIGH to data invalid WEHDNV time t BLS HIGH ...

  • Page 61

    ... See Figure 18. LPC2468 Product data sheet 3 3.6 V, EMC Dynamic Read Config Register = 0x0 DD(DCDC)(3V3) DD(3V3) Conditions All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro Min Typ Max [1] - 1.05 1.76 [1] 0.1 1. ...

  • Page 62

    ... T [1] [1] -  [1] 2 [1] 2 [1] [1] - 3 [1] All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro Typ Max  1 cy(CCLK)  cy(CCLK) cy(CCLK)  1 cy(CCLK) 2 cy(CCLK) cy(CCLK)  ...

  • Page 63

    ... OELOEH t BLSLAV t CSLAV t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro t CSHOEH t h(D) t OEHANV t CSHBLSH 002aad955 t WEHANV t BLSHANV t WEHDNV t BLSHDNV 002aad956 © NXP B.V. 2011. All rights reserved. ...

  • Page 64

    ... All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 Single-chip 16-bit/32-bit micro extended source EOP width: t receiver EOP width: t sampling edges 002aad326 t h(XXX su(D) h(D) LPC2468 FEOPT , t EOPR1 EOPR2 002aab561 002aad636 © NXP B.V. 2011. All rights reserved ...

  • Page 65

    ... All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 Single-chip 16-bit/32-bit micro Min Typ [1][2][ [1][ [1][ [1][ [1][ [ 19. LPC2468 Max Unit V V DDA 1 pF 1 LSB 2 LSB 3 LSB 0.5 % 4 LSB 40 k Figure 19. © NXP B.V. 2011. All rights reserved ...

  • Page 66

    ... All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 Single-chip 16-bit/32-bit micro (1) 1018 1019 1020 1021 1022 1023 − i(VREF) SSA 1 LSB = 1024 LPC2468 offset gain error error 1024 002aae604 © NXP B.V. 2011. All rights reserved ...

  • Page 67

    ... NXP Semiconductors AD0[y] Fig 20. Suggested ADC interface - LPC2468 AD0[y] pin LPC2468 Product data sheet LPC2XXX 20 kΩ SAMPLE SSIO, SSCORE All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro R vsi ...

  • Page 68

    ... G C load capacitance L R load resistance L LPC2468 Product data sheet   +85 C unless otherwise specified Conditions All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro Min Typ Max  1 0 0.6 ...

  • Page 69

    ... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions LPC24XX Fig 21. LPC2468 USB interface on a self-powered device LPC24XX Fig 22. LPC2468 USB interface on a bus-powered device LPC2468 Product data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1.5 kΩ V BUS Ω USB_D Ω ...

  • Page 70

    ... RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 23. LPC2468 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2468 Product data sheet RESET_N ADR/PSW OE_N/INT_N V DD ...

  • Page 71

    ... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 24. LPC2468 USB OTG port configuration: VP_VM mode LPC2468 Product data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1302 ADR/PSW SPEED SUSPEND SCL SDA INT_N ...

  • Page 72

    ... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 V BUS Fig 25. LPC2468 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2468 Product data sheet Ω 33 Ω 15 kΩ 15 kΩ ENA 5 V LM3526 ...

  • Page 73

    ... USB_D+2 USB_D−2 USB_UP_LED2 Fig 26. LPC2468 USB OTG port configuration: USB port 1 host, USB port 2 host 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...

  • Page 74

    ... X2 Maximum crystal series resistance < 300  < 300  < 300  < 300  < 200  < 100  < 160  < 60  < 80  LPC2468 Figure 28 and in and 002aag469 External load capacitors ...

  • Page 75

    ... R S 002aaf495 evaluation Figure 29. Since the feedback resistance is and C need to be connected the typical load L and C X1 External load capacitors LPC2468 , X1 CX2 C P Table 22 specified Parasitics L /C components © NXP B.V. 2011. All rights reserved. ...

  • Page 76

    ... Rev. 6.1 — 6 September 2011 Single-chip 16-bit/32-bit micro , and C should be chosen smaller weak pull-up pull-up enable weak pull-down select analog input LPC2468 , and C in case ESD PIN ESD V SS 002aaf496 © NXP B.V. 2011. All rights reserved ...

  • Page 77

    ... NXP Semiconductors 14.6 Reset pin configuration Fig 31. Reset pin configuration LPC2468 Product data sheet reset GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro ESD ESD V SS 002aaf274 © ...

  • Page 78

    ... All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 Single-chip 16-bit/32-bit micro detail 0.75 1.43 1 0.12 0.08 0.08 0.45 1.08 EUROPEAN PROJECTION LPC2468 SOT459 θ θ 1. 1.08 0 ISSUE DATE 00-02-06 03-02-20 © NXP B.V. 2011. All rights reserved ...

  • Page 79

    ... All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 Single-chip 16-bit/32-bit micro detail 0.08 0.12 0.1 EUROPEAN PROJECTION LPC2468 SOT950 ISSUE DATE 06-06-01 06-06-14 © NXP B.V. 2011. All rights reserved ...

  • Page 80

    ... Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 81

    ... Product data sheet Product data sheet Preliminary data sheet Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro Change notice Supersedes - LPC2468 v.6 - LPC2468 v.5 . stg typ value from 0.5V to 0.05V DD(3V3) - LPC2468 v.4 - LPC2468 v ...

  • Page 82

    ... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 83

    ... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

  • Page 84

    ... Electrical pin characteristics Dynamic characteristics 11.1 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 57 11.2 I/O pins 11.3 USB interface 11.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 58 All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 6 September 2011 LPC2468 Single-chip 16-bit/32-bit micro 2 S-bus serial I/O controllers . . . . . . . . . . . . . 36 © NXP B.V. 2011. All rights reserved. continued >> ...

  • Page 85

    ... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2468 All rights reserved. Date of release: 6 September 2011 Document identifier: LPC2468 ...