XA-G30

Manufacturer Part NumberXA-G30
DescriptionThe Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for hi
ManufacturerNXP Semiconductors
XA-G30 datasheet
 
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XA-G30
XA 16-bit microcontroller family
512 B RAM, watchdog, 2 UARTs
Product data
Replaces datasheet XA-G3 of 2001 Jun 25
hilips
Semiconductors
INTEGRATED CIRCUITS
2002 Mar 25

XA-G30 Summary of contents

  • Page 1

    ... XA-G30 XA 16-bit microcontroller family 512 B RAM, watchdog, 2 UARTs Product data Replaces datasheet XA-G3 of 2001 Jun 25 hilips Semiconductors INTEGRATED CIRCUITS 2002 Mar 25 ...

  • Page 2

    ... SPECIFIC FEATURES OF THE XA-G30 ORDERING INFORMATION ...

  • Page 3

    ... Low power operation, which is intrinsic to the XA architecture, includes power-down and idle modes. More detailed information on the core is available in the XA User Guide. SPECIFIC FEATURES OF THE XA-G30 20-bit address range, 1 megabyte each program and data space. (Note that the XA architecture supports bit addresses.) 2 5.5 V operation ...

  • Page 4

    ... SU01652 XTAL1 XTAL2 RST EA/WAIT PSEN ALE 2 Product data XA-G30 LQFP Function Pin Function P1.5/TxD1 23 P2.5/A17D13 P1.6/T2 24 P2.6/A18D14 P1.7/T2EX 25 P2.7/A19D15 RST 26 PSEN P3.0/RxD0 27 ALE/PROG P3.1/TxD0 29 EA/WAIT P3.2/INT0 30 P0 ...

  • Page 5

    ... Philips Semiconductors XA 16-bit microcontroller family 512 B RAM, watchdog, 2 UARTs BLOCK DIAGRAM 512 BYTES STATIC RAM PORT 0 PORT 1 PORT 2 PORT 3 2002 Mar 25 XA CPU Core SFR BUS Data Bus WATCHDOG 3 Product data XA-G30 UART0 UART1 TIMER 0 & TIMER 1 TIMER 2 TIMER SU01654 ...

  • Page 6

    ... Timer 1 external input, or timer 1 overflow output. The value on this pin is latched as the external reset input is released and defines the default external data bus width (BUSW 8-bit bus and 1 = 16-bit bus. WRL (P3.6): External data memory low byte write strobe. RD (P3.7): External data memory read strobe. 4 Product data XA-G30 ...

  • Page 7

    ... The value on the EA pin is latched as the external reset input is released and applies during later execution. When latched external program memory is used exclusively. EA must be LOW since the XA-G30 does not have on-chip code memory. After reset is released, this pin takes on the function of bus Wait input. If Wait is asserted high during any external bus access, that cycle will be extended until Wait is released ...

  • Page 8

    ... ESWEN R6SEG R5SEG R4SEG 47A — SWE7 SWE6 SWE5 6 Product data XA-G30 RESET RESET VALUE VALUE LSB 39B 39A 399 398 INT1 INT0 TxD0 RxD0 FF Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 ...

  • Page 9

    ... The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes. 7. The XA-G30 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide . All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte. ...

  • Page 10

    ... Philips Semiconductors XA 16-bit microcontroller family 512 B RAM, watchdog, 2 UARTs XA-G30 TIMER/COUNTERS The XA has two standard 16-bit enhanced Timer/Counters: Timer 0 and Timer 1. Additionally, it has a third 16-bit Up/Down timer/counter, T2. A central timing generator in the XA core provides the time-base for all XA Timers and Counters. The timer/event counters can perform the following functions: – ...

  • Page 11

    ... When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator fact, in any application not requiring an interrupt. TR1 TF0 TR0 IE1 IT1 9 Product data XA-G30 LSB IE0 IT0 SU00604C ...

  • Page 12

    ... TL2 and TH2, respectively. A logic ‘0’ at pin T2EX causes Timer 2 to count down. When counting down, the timer value is compared to the 16-bit value contained in T2CAPH and T2CAPL. When the value is equal, the 10 Product data XA-G30 LSB RL2 ...

  • Page 13

    ... T2EX pin X X — — — — T1OE — RCLK1 TCLK1 — — Figure 6. Timer 2 Mode Control (T2MOD) 11 Product data XA-G30 TCLK MODE Timer off (stopped) 16-bit capture Baud rate generator LSB — T0OE SU00612B LSB T2OE DCEN SU00610B ...

  • Page 14

    ... T2CAPL T2CAPH Control (DOWN COUNTING RELOAD VALUE) FFH FFH OVERFLOW TL2 TH2 T2CAPL T2CAPH (UP COUNTING RELOAD VALUE) Figure 9. Timer 2 Auto Reload Mode (DCEN = 1) 12 Product data XA-G30 TF2 Timer 2 Interrupt EXF2 SU00704 TF2 Timer 2 Interrupt EXF2 SU00705 TOGGLE EXF2 TF2 INTERRUPT ...

  • Page 15

    ... When coming out of a hardware reset, the software should load the autoload register and then feed the watchdog (cause an autoload). If the watchdog is running and happens to underflow at the time the external RESET is applied, the watchdog time-out flag will be cleared. 13 Product data XA-G30 4096 t and the OSC PRE0 DIVISOR ...

  • Page 16

    ... Timeout flag WDCON.0 — UARTs The XA-G30 includes 2 UART ports that are compatible with the enhanced UART used on the 8xC51FB. Baud rate selection is somewhat different due to the clocking scheme used for the XA timers. Some other enhancements have been made to UART operation. ...

  • Page 17

    ... TI_n flag, the interrupt system may have to be temporarily disabled during that sequence by clearing, then setting the EA bit in the IEL register. Note Regarding Older XA-G30 Devices Older versions of the XA-G30, XA-G37, and XA-G35 emulation bondout devices do not have the double buffering feature enabled. Contact factory for details. 15 ...

  • Page 18

    ... T2CON 0x418 T2MOD 0x419 Prescaler Select for Timer Clock (TCLK) SCR 0x440 — — — — FEn (See also Figure 13 regarding Framing Error flag) 16 Product data XA-G30 bit5 bit4 RCLK0 TCLK0 bit5 bit4 RCLK1 TCLK1 bit3 bit2 PT1 PT0 LSB BRn ...

  • Page 19

    ... Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature. 17 Product data XA-G30 1100 0000 1111 1101 = 1100 00X0 1100 0000 ...

  • Page 20

    ... FEn BRn Figure 13. UART Framing Error Detection SM0_n SM1_n SM2_n REN_n COMPARATOR 18 Product data XA-G30 LSB TB8 RB8 TI RI SU00597C ONLY IN STOP MODE 2, 3 BIT if 0, sets FE SnSTAT OEn STINTn SU00598 D7 D8 SnCON TB8_n ...

  • Page 21

    ... POWER REDUCTION MODES The XA-G30 supports Idle and Power Down modes of power reduction. The idle mode leaves some peripherals running to allow them to wake up the processor when an interrupt is generated. The power down mode stops the oscillator in order to minimize power. ...

  • Page 22

    ... IEL or IEH registers). Only three bits of the IPA register values are used on the XA-G30. Each event interrupt can be set to occur at one of 8 priority levels via bits in the Interrupt Priority (IP) registers, IPA0 through IPA5 ...

  • Page 23

    ... – 0. 5.5 V must be externally limited as follows V.) DD vs. Frequency Product data XA-G30 RATING UNIT –55 to +125 C –65 to +150 +13.0 V –0 +0 1.5 W LIMITS UNIT UNIT MIN TYP MAX – ...

  • Page 24

    ... WAIT hold after bus strobe (RD, WR, or PSEN) assertion WTL NOTES ON PAGE 23. 2002 Mar 25 PARAMETER PARAMETER PARAMETER PARAMETER 22 Product data XA-G30 VARIABLE CLOCK UNIT UNIT MIN MAX 0 30 MHz 0 30 MHz 0 25 MHz 1 0.5 ...

  • Page 25

    ... For a bus cycle with an ALE the total bus cycle duration (2 if CRA1 CRA1 CRA1/0 = 10, and 5 if CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5). Example: If CRA1 and ALEW = 1, the – (1 2002 Mar PARAMETER PARAMETER 23 Product data XA-G30 VARIABLE CLOCK UNIT UNIT MIN MAX ( – ...

  • Page 26

    ... This parameter is provided for peripherals that have the data clocked in on the falling edge of the WR strobe. This is not usually the case, and in most applications this parameter is not used. 6. Please note that the XA-G30 requires that extended data bus hold time (WM0 = used with external bus write cycles. 2002 Mar 25 ...

  • Page 27

    ... INSTR IN is either D0–D7 or D0–D15, depending on the bus width ( bits). Figure 17. External Program Memory Read Cycle (Non-ALE Cycle) 2002 Mar 25 t LLPL t PLPH t PLIV t LLAX t PXIZ t PLAZ t PXIX * INSTR IN t IXUA t AVIVA A1–A3 * INSTR A1–A3, A12–19 25 Product data XA-G30 SU00946 t AVIVB A0 or A1–A3, A12–19 SU00707 ...

  • Page 28

    ... Figure 19. External Data Memory Read Cycle (Non-ALE Cycle) 8 Bit Bus Only 2002 Mar LLRL RLRH t RHDZ t RLDV t RHDX * DATA AVDVA A0 or A1–A3, A12–A19 D0–D7 A0–A3, A12–A19 26 Product data XA-G30 DXUA SU00947 * DATA IN t AVDVB A0–A3, A12–A19 SU00708A ...

  • Page 29

    ... RD, OR PSEN) t WTH 2002 Mar WLWH LLWL t QVWX * DATA OUT A1–A3, A12–A19 Figure 20. External Data Memory Write Cycle (The dashed line shows the strobe without WAIT.) t WTL Figure 21. WAIT Signal Timing 27 Product data XA-G30 t WHQX UAWH SU00584C SU00709A ...

  • Page 30

    ... DD Figure 23. AC Testing Input/Output +0.1V TIMING REFERENCE POINTS –0.1V /V level occurs Figure 24. Float Waveform (NC) CLOCK SIGNAL SU00591B Figure 26 Product data XA-G30 SU00842 SU00703A V –0. +0. 20mA SU00011 RST EA XTAL2 ...

  • Page 31

    ... Frequency 3.0 V (typical –0.5 0.7V DD 0.2V –0 CHCX CHCL CLCX CLCH t CL Tests in Active and Idle Modes 5ns CLCH CHCL 29 Product data XA-G30 MAX. I (ACTIVE) DD TYPICAL I (ACTIVE) DD MAX. I (IDLE) DD TYPICAL I (IDLE SU01655 TYPICAL I (ACTIVE) DD TYPICAL I (IDLE SU01656 SU00608A ...

  • Page 32

    ... Philips Semiconductors XA 16-bit microcontroller family 512 B RAM, watchdog, 2 UARTs Figure 30. I 2002 Mar RST EA (NC) XTAL2 XTAL1 V SS SU00585A Test Condition, Power Down Mode DD All other pins are disconnected 5 Product data XA-G30 ...

  • Page 33

    ... Philips Semiconductors XA 16-bit microcontroller family 512 B RAM, watchdog, 2 UARTs LQFP44: plastic low profile quad flat package; 44 leads; body 1.4 mm 2002 Mar 25 31 Product data XA-G30 SOT389-1 ...

  • Page 34

    ... Philips Semiconductors XA 16-bit microcontroller family 512 B RAM, watchdog, 2 UARTs PLCC44: plastic leaded chip carrier; 44 leads 2002 Mar 25 32 Product data XA-G30 SOT187-2 ...

  • Page 35

    ... B RAM, watchdog, 2 UARTs REVISION HISTORY Date CPCN 2002 Mar 25 9397 750 09576 2001 Jun 25 9397 750 08554 2002 Mar 25 Description – Converted document into a G30-only data sheet – Improved Supply Current I DD – Corrected typical Previous release 33 Product data XA-G30 ...

  • Page 36

    ... Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. hilips Semiconductors 2002 Mar 25 Fax: + 24825 Document order number: 34 Product data XA-G30 Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 03-02 9397 750 09576 ...