LPC2458 NXP Semiconductors, LPC2458 Datasheet

NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace

LPC2458

Manufacturer Part Number
LPC2458
Description
NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer
NXP Semiconductors
Datasheet
1. General description
2. Features and benefits
NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2458 has 512 kB of on-chip high-speed flash memory. This
flash memory includes a special 128-bit wide memory interface and accelerator
architecture that enables the CPU to execute sequential instructions from flash memory at
the maximum 72 MHz system clock rate. This feature is available only on the LPC2000
ARM microcontroller family of products. The LPC2458 can execute both 32-bit ARM and
16-bit Thumb instructions. Support for the two instruction sets means engineers can
choose to optimize their application for either performance or code size at the sub-routine
level. When the core executes instructions in Thumb state it can reduce code size by
more than 30 % with only a small loss in performance while executing instructions in ARM
state maximizes core performance.
The LPC2458 microcontroller is ideal for multi-purpose communication applications. It
incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed
Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area
Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I
interfaces, and an I
interfaces are the following feature components; an on-chip 4 MHz internal precision
oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for
Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an
External Memory Controller (EMC). These features make this device optimally suited for
communication gateways and protocol converters. Complementing the many serial
communication controllers, versatile clocking capabilities, and memory features are
various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external
interrupt pins, and up to 136 fast GPIO lines. The LPC2458 connects 64 of the GPIO pins
to the hardware based Vector Interrupt Controller (VIC) that means these external inputs
can generate edge-triggered interrupts. All of these features make the LPC2458
particularly suitable for industrial control and medical systems.
LPC2458
Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN,
ISP/IAP, USB 2.0 device/host/OTG, external memory interface
Rev. 4 — 1 September 2011
ARM7TDMI-S processor, running at up to 72 MHz.
512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
98 kB on-chip SRAM includes:
64 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
2
S interface. Supporting this collection of serial communications
Product data sheet
2
C

Related parts for LPC2458

LPC2458 Summary of contents

Page 1

... ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 136 fast GPIO lines. The LPC2458 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC) that means these external inputs can generate edge-triggered interrupts ...

Page 2

... C-bus interfaces (one with open-drain and two with standard port pins (Inter-IC Sound) interface for digital audio input or output. It can be used with All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

Page 3

... Medical systems  Protocol converter  Communications 4. Ordering information Table 1. Ordering information Type number Package Name LPC2458FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12  12  0.8 mm 4.1 Ordering options Table 2. Ordering options Type number Flash (kB) LPC2458FET180 512 LPC2458 ...

Page 4

... AD0 A/D CONVERTER D/A CONVERTER AOUT VBAT 2 kB BATTERY RAM power domain 2 RTCX1 RTC RTCX2 OSCILLATOR ALARM WATCHDOG TIMER SYSTEM CONTROL Fig 1. LPC2458 block diagram LPC2458 Product data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 64 kB 512 kB TEST/DEBUG SRAM FLASH INTERFACE ...

Page 5

... V 6 DD(3V3) 9 P1[17]/ENET_MDIO 10 LPC2458 Product data sheet ball A1 index area LPC2458 pinning TFBGA180 package Pin Symbol P3[2]/D2 3 P0[3]/RXD0 P3[8]/D8 7 P1[10]/ENET_RXD1 V 11 P0[4]/I2SRX_CLK/RD2/ SSCORE CAP2[0] P1[12]/ENET_RXD3 MCIDAT3/PCAP0[0] P3[11]/D11 3 P3[10]/D10 P1[8]/ENET_CRS_DV/ 7 P1[2]/ENET_TXD2/ ENET_CRS MCICLK/PWM0[1] P1[6]/ENET_TX_CLK/ 11 P0[5]/I2SRX_WS/TD2/ MCIDAT0/PWM0[4] ...

Page 6

... P2[0]/PWM1[1]/TXD1/ SSEL1/MAT2[0] TRACECLK - 16 - P3[5]/D5 4 P0[25]/AD0[2]/ I2SRX_SDA/TXD3 P4[31]/CS1 8 P4[14]/A14 P2[2]/PWM1[3 DD(3V3) CTS1/PIPESTAT1 - P3[6]/D6 SSA 8 P4[11]/A11 12 P2[5]/PWM1[6]/ DTR1/TRACEPKT0 - 16 - P3[7]/D7 4 P3[15]/D15 8 P2[7]/RD2/ 12 P4[10]/A10 RTS1/TRACEPKT2 - SSCORE SSIO 8 P2[9]/ 12 P4[9]/A9 USB_CONNECT1/ RXD2/EXTIN0 - 16 - RTCX2 4 P0[12]/USB_PPWR2/ MISO1/AD0[6] 8 LPC2458 © NXP B.V. 2011. All rights reserved ...

Page 7

... USB_HSTEN1/MAT1[ n.c. DD(3V3 P3[25]/MAT0[0]/ 4 P3[23]/CAP0[0]/ PWM1[2] PCAP1[0] P4[1]/A1 8 P4[2]/A2 P2[13]/EINT3/ 12 P2[11]/EINT1/ MCIDAT3/I2STX_SDA MCIDAT1/I2STX_CLK - 16 - P3[24]/CAP0[1]/ 4 P0[30]/USB_D1 PWM1[1] P1[23]/USB_RX_DP1/ 8 P2[21]/DYCS1 PWM1[4]/MISO0 P0[1]/TD1/RXD3/SCL1 12 P4[16]/A16 - 16 - P2[18]/CLKOUT0 4 V SSIO P1[24]/USB_RX_DM1/ 8 P1[26]/USB_SSPND1/ PWM1[5]/MOSI0 PWM1[6]/CAP0[0] P2[17]/RAS 12 P0[11]/RXD2/SCL2/ MAT3[ LPC2458 © NXP B.V. 2011. All rights reserved ...

Page 8

... Corresponds to the signal WS in the I I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro 2 S-bus specification. 2 S-bus specification. 2 S-bus specification ...

Page 9

... RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro 2 S-bus specification. © NXP B.V. 2011. All rights reserved ...

Page 10

... I2SRX_SDA — Receive data driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I O TXD3 — Transmitter output for UART3. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro 2 S-bus specification. 2 S-bus specification. ...

Page 11

... ENET_TX_CLK — Ethernet Transmit Clock (MII interface). I/O MCIDAT0 — Data line 0 for SD/MMC interface. O PWM0[4] — Pulse Width Modulator 0, output 4. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro 2 C-bus compliance). 2 C-bus compliance). © NXP B.V. 2011. All rights reserved. ...

Page 12

... USB_PPWR1 — Port Power enable signal for USB port 1. I CAP1[1] — Capture input for Timer 1, channel 1. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

Page 13

... MAT0[1] — Match output for Timer 0, channel 0. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 Single-chip 16-bit/32-bit micro 2 C serial clock (OTG transceiver serial data (OTG transceiver). LPC2458 © NXP B.V. 2011. All rights reserved ...

Page 14

... PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. O TRACEPKT1 — Trace Packet, bit 1. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

Page 15

... O CLKOUT0 — SDRAM clock 0. I/O P2[19] — General purpose digital input/output pin. O CLKOUT1 — SDRAM clock 1. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro 2 S-bus specification. 2 S-bus specification. 2 S-bus specification. © NXP B.V. 2011. All rights reserved. ...

Page 16

... D10 — External memory data line 10. I/O P3[11] — General purpose digital input/output pin. I/O D11 — External memory data line 11. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

Page 17

... P4[6] — General purpose digital input/output pin. I/O A6 — External memory address line 6. I/O P4[7] — General purpose digital input/output pin. I/O A7 — External memory address line 7. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

Page 18

... RXD3 — Receiver input for UART3. I/O P4[30] — General purpose digital input/output pin. O CS0 — LOW active Chip Select 0 signal. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

Page 19

... RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2458 being in Reset state. I external reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...

Page 20

... AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order. The LPC2458 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. ...

Page 21

... ARM code while retaining most of the ARM’s performance. 7.2 On-chip flash programming memory The LPC2458 incorporates 512 kB flash memory system. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port (UART0). The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field and firmware upgrades ...

Page 22

... NXP Semiconductors 7.3 On-chip SRAM The LPC2458 includes a SRAM memory reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits SRAM block serving as a buffer for the Ethernet controller and SRAM associated with the second AHB can be used both for data and code storage ...

Page 23

... FLASH REMAPPED FROM ON-CHIP FLASH) RESERVED ADDRESS SPACE ON-CHIP STATIC RAM 1.0 GB SPECIAL REGISTERS RESERVED ADDRESS SPACE ON-CHIP NON-VOLATILE MEMORY 0.0 GB LPC2458 memory map All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro 0xFFFF FFFF 0xF000 0000 0xE000 0000 ...

Page 24

... External memory controller The LPC2458 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals ...

Page 25

... Separate reset domains allow auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.8 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2458 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions ...

Page 26

... The value of the output register may be read back as well as the current state of the port pins. LPC2458 use accelerated GPIO functions: • GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved. • ...

Page 27

... The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2458 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory via the EMC, as well as the SRAM located on another AHB ...

Page 28

... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, LPC2458 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with the DMA RAM all non-control endpoints. ...

Page 29

... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. LPC2458 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro 2 C interface © NXP B.V. 2011. All rights reserved ...

Page 30

... Optional conversion on transition of input pin or Timer Match signal • Individual result registers for each ADC channel to reduce interrupt overhead 7.14 10-bit DAC The DAC allows the LPC2458 to generate a variable analog output. The maximum output value of the DAC is V 7.14.1 Features • 10-bit DAC • ...

Page 31

... UART3 includes an IrDA mode to support infrared communication. 7.16 SPI serial I/O controller The LPC2458 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master ...

Page 32

... The I be controlled by more than one bus master connected to it. 2 The I C-bus implemented in LPC2458 supports bit rates up to 400 kbit/s (Fast I 7.19.1 Features • standard I • ...

Page 33

... Controls include reset, stop and mute options separately for I 7.21 General purpose 32-bit timers/external event counters The LPC2458 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers ...

Page 34

... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2458. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...

Page 35

... The RTC is a set of counters for measuring time when system power is on, and optionally when power is off. It uses little power in Power-down and Deep power-down modes. On the LPC2458, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock. The RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3 ...

Page 36

... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy. Upon power-up or any chip reset, the LPC2458 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.25.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL ...

Page 37

... PLL to lock, then connect to the PLL as a clock source. 7.25.3 Wake-up timer The LPC2458 begins operation at power-up and when awakened from Power-down and Deep power-down modes by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...

Page 38

... NXP Semiconductors 7.25.4 Power control The LPC2458 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements ...

Page 39

... If power is supplied to the LPC2458 during Deep power-down mode, wake-up can be caused by the RTC Alarm interrupt or by external Reset. While in Deep power-down mode, external device power may be removed. In this case, the LPC2458 will start up when external power is restored ...

Page 40

... Code security (Code Read Protection - CRP) This feature of the LPC2458 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. ...

Page 41

... If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.26.4 AHB The LPC2458 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB SRAM ...

Page 42

... The JTAG clock (TCK) must be slower than interface to operate. 7.27.2 Embedded trace Since the LPC2458 have significant amounts of on-chip memories not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port ...

Page 43

... All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro Min Max Unit 3.0 3.6 V 3.0 3.6 V 0.5 +4 ...

Page 44

... All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 Single-chip 16-bit/32-bit micro (C), can be calculated using the following j and V . The I/O power dissipation Min Typ - -  C unless otherwise specified 45.5 38.3 33.8 38 33.5 29.8 8.9 12 LPC2458 (1) Max Unit C 125 © NXP B.V. 2011. All rights reserved ...

Page 45

... CCLK = 10 MHz CCLK = 72 MHz all peripherals enabled; PCLK = CCLK CCLK = 10 MHz CCLK = 72 MHz [ 3.3 V; DD(DCDC)(3V3 C T amb [3] [4] [3] Deep power-down mode All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro [1] Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 2.0 3.3 3.6 2.5 3 ...

Page 46

... DDA < V < DD(3V3 OLS DD(3V3 All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro [1] Min Typ - - - - - - - - [5][6 0.4 -  [ DD(3V3) 0 ...

Page 47

... GND with 33  series resistor; steady state drive drops below 1  i(VBAT) amb is grounded. DD(3V3 All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro [1] Min Typ Max 0.5 1.8 1.95 0.5 1.8 1.95 0.5 1.8 1.95  ...

Page 48

... All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 Single-chip 16-bit/32-bit micro V = 3.3 V DD(3V3 3.0 V DD(3V3 temperature (° C. versus temperature in Power-down mode DD(IO temperature (° C. amb versus temperature in Power-down BAT LPC2458 002aae049 85 002aae050 85 © NXP B.V. 2011. All rights reserved ...

Page 49

... 3 DD(3V3) DD(DCDC)(3V3) amb I/O maximum supply current I DD(IO) mode All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro 002aae051 35 60 temperature (°C) at different temperatures DD(DCDC)pd(3V3) 002aae046 35 60 temperature (° C. ...

Page 50

... Deep power-down mode All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 Single-chip 16-bit/32-bit micro temperature (° C amb versus temperature in Deep BAT temperature (°C) DD(DCDC)dpd(3V3) LPC2458 002aae047 85 002aae048 85 versus © NXP B.V. 2011. All rights reserved ...

Page 51

... 0.2 Conditions 3.3 V; standard port pins. DD(3V3) All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro 002aaf112 16 I (mA) OH versus HIGH-level output source current OH 002aaf111 °C 25 °C −40 °C 0.4 ...

Page 52

... SPI Master mode; see Figure CHCL CLCX CLCH T cy(clk) = 200 mV) i(RMS) All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro [1] [2] Min Typ Max 1000  0 cy(clk)  0.4 ...

Page 53

... Figure 15 see Figure must reject as EOP; see Figure 15 must accept as EOP; see Figure 15 All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro [2] Min Typ Max 3.96 4.02 4.04 - 32.768 - Min Typ Max 3 ...

Page 54

... V to 3.6 V; all voltages are measured with respect to DD(3V3) Conditions [1] [2] powered; < 100 cycles unpowered; < 100 cycles sector or multiple consecutive sectors [2] All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro Min Typ Max 10000 100000 - ...

Page 55

Static external memory interface Table 15. Dynamic characteristics: Static external memory interface    pF amb DD(DCDC)(3V3) Symbol Parameter Conditions [1] Common to read and write ...

Page 56

Table 15. Dynamic characteristics: Static external memory interface    pF amb DD(DCDC)(3V3) Symbol Parameter Conditions t WE HIGH to data invalid WEHDNV time t BLS HIGH ...

Page 57

... See Figure 17. LPC2458 Product data sheet 3 3.6 V, EMC Dynamic Read Config Register = 0x0 DD(DCDC)(3V3) DD(3V3) Conditions All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro Min Typ Max [1] - 1.05 1.76 [1] 0.1 1. ...

Page 58

... T [1] [1] -  [1] 2 [1] 2 [1] [1] - 3 [1] All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro Typ Max  1 cy(CCLK)  cy(CCLK) cy(CCLK)  1 cy(CCLK) 2 cy(CCLK) cy(CCLK)  ...

Page 59

... OELOEH t BLSLAV t CSLAV t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro t CSHOEH t h(D) t OEHANV t CSHBLSH 002aad955 t WEHANV t BLSHANV t WEHDNV t BLSHDNV 002aad956 © NXP B.V. 2011. All rights reserved. ...

Page 60

... All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 Single-chip 16-bit/32-bit micro extended source EOP width: t receiver EOP width: t sampling edges 002aad326 t h(XXX su(D) h(D) LPC2458 FEOPT , t EOPR1 EOPR2 002aab561 002aad636 © NXP B.V. 2011. All rights reserved ...

Page 61

... All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 Single-chip 16-bit/32-bit micro Min Typ [1][2][ [1][ [1][ [1][ [1][ [ 18. LPC2458 Max Unit V V DDA 1 pF 1 LSB 2 LSB 3 LSB 0.5 % 4 LSB 40 k Figure 18. © NXP B.V. 2011. All rights reserved ...

Page 62

... All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 Single-chip 16-bit/32-bit micro (1) 1018 1019 1020 1021 1022 1023 − i(VREF) SSA 1 LSB = 1024 LPC2458 offset gain error error 1024 002aae604 © NXP B.V. 2011. All rights reserved ...

Page 63

... NXP Semiconductors AD0[y] Fig 19. Suggested ADC interface - LPC2458 AD0[y] pin LPC2458 Product data sheet LPC2XXX 20 kΩ SAMPLE SSIO, SSCORE All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro R vsi ...

Page 64

... G C load capacitance L R load resistance L LPC2458 Product data sheet   +85 C unless otherwise specified Conditions All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro Min Typ Max  1 0 0.6 ...

Page 65

... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions LPC24XX Fig 20. LPC2458 USB interface on a self-powered device LPC24XX Fig 21. LPC2458 USB interface on a bus-powered device LPC2458 Product data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1.5 kΩ V BUS Ω USB_D Ω ...

Page 66

... RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 22. LPC2458 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2458 Product data sheet RESET_N ADR/PSW OE_N/INT_N V DD ...

Page 67

... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 23. LPC2458 USB OTG port configuration: VP_VM mode LPC2458 Product data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1302 ADR/PSW SPEED SUSPEND SCL SDA INT_N ...

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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 V BUS Fig 24. LPC2458 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2458 Product data sheet Ω 33 Ω 15 kΩ 15 kΩ ENA 5 V LM3526 ...

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... USB_D+2 USB_D−2 USB_UP_LED2 Fig 25. LPC2458 USB OTG port configuration: USB port 1 host, USB port 2 host 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...

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... X2 Maximum crystal series resistance < 300  < 300  < 300  < 300  < 200  < 100  < 160  < 60  < 80  LPC2458 Figure 27 and in and 002aag469 External load capacitors ...

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... R S 002aaf495 evaluation Figure 28. Since the feedback resistance is and C need to be connected the typical load L and C X1 External load capacitors LPC2458 , X1 CX2 C P Table 22 specified Parasitics L /C components © NXP B.V. 2011. All rights reserved. ...

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... Rev. 4 — 1 September 2011 Single-chip 16-bit/32-bit micro , and C should be chosen smaller weak pull-up pull-up enable weak pull-down select analog input LPC2458 , and C in case ESD PIN ESD V SS 002aaf496 © NXP B.V. 2011. All rights reserved ...

Page 73

... NXP Semiconductors 14.6 Reset pin configuration Fig 30. Reset pin configuration LPC2458 Product data sheet reset GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro ESD ESD V SS 002aaf274 © ...

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... JEITA All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 Single-chip 16-bit/32-bit micro detail 0.08 0.12 0.1 EUROPEAN PROJECTION LPC2458 SOT570-2 ISSUE DATE 03-03-03 06-03-14 © NXP B.V. 2011. All rights reserved ...

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... Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

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... Added new table. typ value from 0.5V to 0.05V DD(3V3) interface”: Removed “AHB clock interface”: Swapped min/max interface”: Updated t interface”: Removed “AHB interface”: Added new table. Updated bullets. - LPC2458 v.2 - LPC2458 v © NXP B.V. 2011. All rights reserved. . DD(3V3) WEHDNV ...

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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro © NXP B.V. 2011. All rights reserved ...

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... Electrical pin characteristics Dynamic characteristics 11.1 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 53 11.2 I/O pins 11.3 USB interface 11.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 54 All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 September 2011 LPC2458 Single-chip 16-bit/32-bit micro 2 S-bus serial I/O controllers . . . . . . . . . . . . . 32 © NXP B.V. 2011. All rights reserved. continued >> ...

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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2458 All rights reserved. Date of release: 1 September 2011 Document identifier: LPC2458 ...

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