lpc2420

Manufacturer Part Numberlpc2420
DescriptionFlashless 16-bit/32-bit Microcontroller; Ethernet, Can, Isp/iap, Usb 2.0 Device/host/otg, External Memory Interface
ManufacturerNXP Semiconductors
lpc2420 datasheet
 


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LPC2420/2460
Flashless 16-bit/32-bit microcontroller; Ethernet, CAN,
ISP/IAP, USB 2.0 device/host/OTG, external memory interface
Rev. 03 — 20 November 2008
1. General description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2420/2460 is flashless. The LPC2420/2460 can execute both
32-bit ARM and 16-bit Thumb instructions. Support for the two instruction sets means
engineers can choose to optimize their application for either performance or code size at
the sub-routine level. When the core executes instructions in Thumb state it can reduce
code size by more than 30 % with only a small loss in performance while executing
instructions in ARM state maximizes core performance.
The LPC2420/2460 microcontroller is ideal for multi-purpose communication applications.
It incorporates a 10/100 Ethernet Media Access Controller (MAC) (LPC2460 only), a USB
full-speed Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two
Controller Area Network (CAN) channels (LPC2460 only), an SPI interface, two
Synchronous Serial Ports (SSP), three I
this collection of serial communications interfaces are the following feature components;
an on-chip 4 MHz internal precision oscillator, 82/98 kB of total RAM consisting of 64 kB
of local SRAM, 16 kB SRAM for Ethernet (LPC2460 only), 16 kB SRAM for general
purpose DMA, 2 kB of battery powered SRAM, and an External Memory Controller
(EMC). These features make this device optimally suited for communication gateways and
protocol converters. Complementing the many serial communication controllers, versatile
clocking capabilities, and memory features are various 32-bit timers, an improved 10-bit
ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 160 fast GPIO
lines. The LPC2420/2460 connects 64 of the GPIO pins to the hardware based Vector
Interrupt Controller (VIC) that means these external inputs can generate edge-triggered
interrupts. All of these features make the LPC2420/2460 particularly suitable for industrial
control and medical systems.
2. Features
I
ARM7TDMI-S processor, running at up to 72 MHz.
I
82/98 kB on-chip SRAM includes:
N
64 kB of SRAM on the ARM local bus for high performance CPU access.
N
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
(LPC2460 only)
N
16 kB SRAM for general purpose DMA use also accessible by the USB.
N
2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
I
Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet
DMA, and USB DMA with no contention (LPC2460 only).
Preliminary data sheet
2
2
C interfaces, and an I
S interface. Supporting

lpc2420 Summary of contents

  • Page 1

    ... ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 160 fast GPIO lines. The LPC2420/2460 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC) that means these external inputs can generate edge-triggered interrupts ...

  • Page 2

    ... Preliminary data sheet 2 C-bus interfaces (one with open-drain and two with standard port pins (Inter-IC Sound) interface for digital audio input or output. It can be used with Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 3

    ... Medical systems I Protocol converter I Communications 4. Ordering information Table 1. Ordering information Type number Package Name LPC2420FBD208 LQFP208 LPC2460FBD208 LQFP208 LPC2460FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 15 4.1 Ordering options Table 2. Ordering options Type number Flash (kB) LPC2420FBD208 N/A ...

  • Page 4

    ... A/D CONVERTER D/A CONVERTER AOUT VBAT 2 kB BATTERY RAM power domain 2 RTCX1 RTC RTCX2 OSCILLATOR ALARM WATCHDOG TIMER SYSTEM CONTROL (1) LPC2460 only. Fig 1. LPC2420/2460 block diagram LPC2420_60_3 Preliminary data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 64 kB TEST/DEBUG SRAM INTERFACE INTERNAL ...

  • Page 5

    ... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC2420/2460 pinning LQFP208 package Fig 3. LPC2460 pinning TFBGA208 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 P3[27]/D27/ 2 CAP1[0]/PWM1[4] 5 P1[4]/ENET_TX_EN 6 9 P1[17]/ENET_MDIO 10 13 P3[20]/D20/ 14 PWM0[5]/DSR1 LPC2420_60_3 Preliminary data sheet 1 LPC2420FBD208 LPC2460FBD208 ...

  • Page 6

    ... TMS V 16 P2[3]/PWM1[4]/ SSIO DCD1/PIPESTAT2 P3[4]/D4 3 P3[29]/D29/ MAT1[0]/PWM1[6] P3[17]/D17/ 16 P2[5]/PWM1[6]/ PWM0[2]/RXD1 DTR1/TRACEPKT0 P0[24]/AD0[1 DD(3V3) I2SRX_WS/CAP3[1] P4[27]/BLS1 16 P2[7]/RD2/ RTS1/TRACEPKT2 Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller Pin Symbol - 4 P3[0]/D0 8 P4[24]/OE 12 P0[4]/I2SRX_CLK/RD2/ CAP2[0] 16 P4[13]/A13 - 4 P0[2]/TXD0 8 P1[10]/ENET_RXD1 12 P0[5]/I2SRX_WS/TD2/ CAP2[1] 16 P4[12]/A12 - 4 P3[12]/D12 ...

  • Page 7

    ... PWM1[1]/CAP1[ SSCORE DD(DCDC)(3V3) P4[17]/A17 15 P4[18]/A18 - - P0[13]/USB_UP_LED2/ 3 P0[28]/SCL0 MOSI1/AD0[7] P0[30]/USB_D 1 7 P2[19]/CLKOUT1 P1[26]/USB_SSPND1/ 11 P2[16]/CAS PWM1[6]/CAP0[0] Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller Pin Symbol 4 V DD(DCDC)(3V3) 17 P4[9]/A9 4 n.c. 17 P4[8]/ SSCORE 17 P0[17]/CTS1/ MISO0/MISO 4 P2[30]/DQMOUT2/ MAT3[2]/SDA2 17 P0[19]/DSR1/ ...

  • Page 8

    ... RXD3 — Receiver input for UART3. 2 I/O SCL1 — clock input/output (this is not an open-drain pin). [1] I/O P0[2] — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller Pin Symbol 16 P4[5]/ P2[26]/CKEOUT2/ MAT3[0]/MISO0 8 P2[20]/DYCS0 ...

  • Page 9

    ... I RXD2 — Receiver input for UART2. 2 I/O SCL2 — clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller 2 S-bus specification . 2 S-bus 2 S-bus specification . 2 S-bus specification . ...

  • Page 10

    ... P0[20] — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. I/O MCICMD — Command line for SD/MMC interface. 2 I/O SCL1 — clock input/output (this is not an open-drain pin). Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 11

    ... I/O Port 1: Port bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the Pin Connect block. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller 2 S-bus specification . 2 S-bus 2 S-bus specifi ...

  • Page 12

    ... P1[11] — General purpose digital input/output pin. I ENET_RXD2 — Ethernet Receive Data 2 (MII interface) (LPC2460 only). I/O MCIDAT2 — Data line 2 for SD/MMC interface. O PWM0[6] — Pulse Width Modulator 0, output 6. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 13

    ... USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver). I USB_PWRD1 — Power Status for USB port 1 (host power switch). O MAT1[0] — Match output for Timer 1, channel 0. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 14

    ... Port 2: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the Pin Connect block. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller 2 C-bus serial clock (OTG transceiver). ...

  • Page 15

    ... TRACEPKT2 — Trace Packet, bit 2. [1] I/O P2[8] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output (LPC2460 only). O TXD2 — Transmitter output for UART2. O TRACEPKT3 — Trace Packet, bit 3. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 16

    ... P2[18] — General purpose digital input/output pin. O CLKOUT0 — SDRAM clock 0. [1] I/O P2[19] — General purpose digital input/output pin. O CLKOUT1 — SDRAM clock 1. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller 2 S-bus specification . 2 S-bus 2 S-bus specification . © NXP B.V. 2008. All rights reserved. ...

  • Page 17

    ... The operation of port 3 pins depends upon the pin function selected via the Pin Connect block. [1] I/O P3[0] — General purpose digital input/output pin. I/O D0 — External memory data line 0. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 18

    ... P3[16] — General purpose digital input/output pin. I/O D16 — External memory data line 16. O PWM0[1] — Pulse Width Modulator 0, output 1. O TXD1 — Transmitter output for UART1. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 19

    ... P3[26] — General purpose digital input/output pin. I/O D26 — External memory data line 26. O MAT0[1] — Match output for Timer 0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 20

    ... A6 — External memory address line 6. [1] I/O P4[7] — General purpose digital input/output pin. I/O A7 — External memory address line 7. [1] I/O P4[8] — General purpose digital input/output pin. I/O A8 — External memory address line 8. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 21

    ... RXD2 — Receiver input for UART2. I/O MOSI1 — Master Out Slave In for SSP1. [1] I/O P4[24] — General purpose digital input/output pin — LOW active Output Enable signal. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 22

    ... RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2420/2460 being in Reset state. [7] I external reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...

  • Page 23

    ... C-bus 400 kHz specification. It requires an external pull-up to provide output 2 C-bus is floating and does not disturb the I Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller , but should be isolated to minimize noise and SSCORE but should be isolated to minimize noise and error. DD(3V3) 2 C-bus lines ...

  • Page 24

    ... NXP Semiconductors 7. Functional description 7.1 Architectural overview The LPC2420/2460 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external memory, and the AMBA APB for connection to other on-chip peripheral functions. ...

  • Page 25

    ... ARM code while retaining most of the ARM’s performance. 7.2 On-chip SRAM The LPC2420/2460 includes a SRAM memory reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. ...

  • Page 26

    ... NXP Semiconductors 3.75 GB Fig 4. LPC2420/2460 memory map 7.4 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...

  • Page 27

    ... External memory controller The LPC2420/2460 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals ...

  • Page 28

    ... Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.7 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2420/2460 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions ...

  • Page 29

    ... The value of the output register may be read back as well as the current state of the port pins. LPC2420/2460 use accelerated GPIO functions: • GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved. • ...

  • Page 30

    ... The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2420/2460 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory via the EMC, as well as the SRAM located on another AHB ...

  • Page 31

    ... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, LPC2420/2460 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with the DMA RAM all non-control endpoints. ...

  • Page 32

    ... Compatible with CAN specification 2.0B, ISO 11898-1 . • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. LPC2420_60_3 Preliminary data sheet Flashless 16-bit/32-bit microcontroller Rev. 03 — 20 November 2008 LPC2420/2460 2 C-bus © NXP B.V. 2008. All rights reserved ...

  • Page 33

    ... Optional conversion on transition of input pin or Timer Match signal • Individual result registers for each ADC channel to reduce interrupt overhead 7.13 10-bit DAC The DAC allows the LPC2420/2460 to generate a variable analog output. The maximum output value of the DAC is V 7.13.1 Features • 10-bit DAC • ...

  • Page 34

    ... UART3 includes an IrDA mode to support infrared communication. 7.15 SPI serial I/O controller The LPC2420/2460 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. ...

  • Page 35

    ... The I be controlled by more than one bus master connected to it. 2 The I C-bus implemented in LPC2420/2460 supports bit rates up to 400 kbit/s (Fast 2 I C-bus). 7.18.1 Features • ...

  • Page 36

    ... Controls include reset, stop and mute options separately for I output. 7.20 General purpose 32-bit timers/external event counters The LPC2420/2460 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers ...

  • Page 37

    ... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2420/2460. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...

  • Page 38

    ... RTC and battery RAM The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down mode. On the LPC2420/2460, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock ...

  • Page 39

    ... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy. Upon power-up or any chip reset, the LPC2420/2460 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.24.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL ...

  • Page 40

    ... PLL to lock, then connect to the PLL as a clock source. 7.24.3 Wake-up timer The LPC2420/2460 begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...

  • Page 41

    ... Each of the peripherals has its own clock divider which provides even better power control. The LPC2420/2460 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the Battery RAM ...

  • Page 42

    ... NXP Semiconductors 7.24.4.4 Power domains The LPC2420/2460 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery RAM. On the LPC2420/2460, I/O pads are powered by the 3 DD(DCDC)(3V3) the CPU and most of the peripherals. ...

  • Page 43

    ... VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts a BOD Reset and generates a Reset (if this reset source is enabled in software) to inactivate the LPC2420/2460 when the voltage on the V below which point the power-on reset circuitry maintains the overall Reset. ...

  • Page 44

    ... NXP Semiconductors 7.26 Emulation and debugging The LPC2420/2460 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself ...

  • Page 45

    ... lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2420/2460 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory. ...

  • Page 46

    ... V tolerant I/O pins; only valid when the V DD(3V3) supply voltage is present [2][3] other I/O pins per supply pin per ground pin based on package heat transfer, not device power consumption human body model; all pins Rev. 03 — 20 November 2008 LPC2420/2460 Min Max Unit 3.0 3.6 V 3.0 3.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +4 ...

  • Page 47

    ... 0 DD(3V3 0 DDA < V < DD(3V3) I Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller [1] Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 [2] 2.0 3.3 3.6 2.5 3.3 V DDA - - 100 ...

  • Page 48

    ... PCLK = CCLK CCLK = 10 MHz CCLK = 72 MHz V = 3.3 V; DD(DCDC)(3V3 amb DC-to-DC converter on DC-to-DC converter off OLS DD(3V3 < V < 3 Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller [1] Min Typ Max - <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> ...

  • Page 49

    ... V range 1 3 GND L pin to GND with 33 series resistor; steady state drive SoftConnect = ON drops below 1 grounded. DD(3V3 and D . Conditions Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller [1] Min Typ 0.2 - 0 [12 1.1 - Min Typ ...

  • Page 50

    ... See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 5. Figure Figure 5. Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller Min Typ [1][ [1][7] ...

  • Page 51

    ... Preliminary data sheet (2) (5) (4) (3) 1 LSB (ideal) 1018 (LSB ) IA ideal ). D ). Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller offset error E O (1) 1019 1020 1021 1022 1023 1024 V V DDA SSA 1 LSB = 1024 002aac046 © NXP B.V. 2008. All rights reserved. ...

  • Page 52

    ... NXP Semiconductors AD0[y] Fig 6. Suggested ADC interface - LPC2420/2460 AD0[y] pin LPC2420_60_3 Preliminary data sheet LPC2XXX 20 k SAMPLE SSIO, SSCORE Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller R vsi AD0[y] V EXT 002aad586 © NXP B.V. 2008. All rights reserved. ...

  • Page 53

    ... DD(3V3) Conditions see Figure 8 see Figure must reject as EOP; see Figure 8 must accept as EOP; see Figure 8 Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller Min Typ Max 8.5 - 13.8 7 109 1.3 - 2.0 160 - 175 2 ...

  • Page 54

    ... Preliminary data sheet Flashless 16-bit/32-bit microcontroller over specified ranges. DD(3V3) Conditions Min cy(clk) T cy(clk 0 amb measured in SPI Master mode; see Figure 9 Rev. 03 — 20 November 2008 LPC2420/2460 [1] [2] Typ Max Unit - 24 MHz - 1000 [3] C ...

  • Page 55

    Table 11. Dynamic characteristics: Static external memory interface pF amb DD(DCDC)(3V3) Symbol Parameter Conditions [1] Common to read and write cycles t CS LOW to address valid CSLAV ...

  • Page 56

    Table 11. Dynamic characteristics: Static external memory interface pF amb DD(DCDC)(3V3) Symbol Parameter Conditions t WE HIGH to data invalid WEHDNV time t BLS HIGH to address BLSHANV ...

  • Page 57

    ... Write cycle parameters t data output valid delay time d(QV) t data output hold time h(Q) LPC2420_60_3 Preliminary data sheet = 3.6 V, AHB clock = 1 MHz DD(DCDC)(3V3) DD(3V3) Conditions Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller Min Typ Max - 1.05 1.76 0.1 1. 1.51 1.95 0.5 1. ...

  • Page 58

    ... CHCL CLCX i(RMS) crossover point crossover point differential data to SE0/EOP skew PERIOD FDEOP t su(SPI_MISO) Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller t CHCX t CLCH T cy(clk) 002aaa907 = 200 mV) extended source EOP width: t receiver EOP width: t sampling edges 002aad326 FEOPT , t ...

  • Page 59

    ... Preliminary data sheet t CSLAV OELAV t OELOEH t BLSLAV t AVCSL t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller t CSHOEH t h(D) t OEHANV t CSHBLSH 002aad955 t WEHANV t BLSHANV t WEHDNV t BLSHDNV 002aad956 © NXP B.V. 2008. All rights reserved ...

  • Page 60

    ... NXP Semiconductors Fig 12. Signal timing 11. Application information 11.1 Suggested USB interface solutions LPC24XX Fig 13. LPC2420/2460 USB interface on a self-powered device LPC2420_60_3 Preliminary data sheet reference clock t d(XXX) output signal (O) input signal (I) V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1 BUS USB_D ...

  • Page 61

    ... NXP Semiconductors LPC24XX Fig 14. LPC2420/2460 USB interface on a bus-powered device LPC2420_60_3 Preliminary data sheet Flashless 16-bit/32-bit microcontroller V DD(3V3 USB_UP_LED 1 BUS USB_D USB_D V V SSIO, SSCORE Rev. 03 — 20 November 2008 LPC2420/2460 USB-B connector 002aad588 © NXP B.V. 2008. All rights reserved. ...

  • Page 62

    ... RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D 1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D 2 USB_UP_LED2 Fig 15. LPC2420/2460 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2420_60_3 Preliminary data sheet RESET_N ADR/PSW OE_N/INT_N V DD SPEED ...

  • Page 63

    ... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 16. LPC2420/2460 USB OTG port configuration: VP_VM mode LPC2420_60_3 Preliminary data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1301 ADR/PSW SPEED SUSPEND SCL SDA ...

  • Page 64

    ... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D 1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D 2 V BUS Fig 17. LPC2420/2460 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2420_60_3 Preliminary data sheet FLAGA ENA OUTA 5 V LM3526-L ...

  • Page 65

    ... USB_D+2 USB_D 2 USB_UP_LED2 Fig 18. LPC2420/2460 USB OTG port configuration: USB port 1 host, USB port 2 host 11.2 Suggested boot memory interface solutions ‘a_m’ and ‘a_b’ in the following figures refer to the highest order address line of the memory chip and the highest order microcontroller’s address line used respectively. ...

  • Page 66

    ... NXP Semiconductors Fig 20. Booting from a single 16-bit memory chip LPC2420_60_3 Preliminary data sheet CS1 16-bit BLS1 MEMORY LB BLS0 IO[15:0] D[15:0] A[a_m:0] A[a_b:1] 002aad323 Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 67

    ... scale (1) ( 0.27 0.20 28.1 28.1 30.15 30.15 0.5 0.17 0.09 27.9 27.9 29.85 29.85 REFERENCES JEDEC JEITA MS-026 Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller detail 0.75 1.43 1 0.12 0.08 0.08 0.45 1.08 EUROPEAN PROJECTION SOT459 ...

  • Page 68

    ... 15.1 15.1 0.8 12.8 12.8 0.15 14.9 14.9 REFERENCES JEDEC JEITA - - - Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller detail 0.08 0.12 0.1 EUROPEAN PROJECTION SOT950 ISSUE DATE ...

  • Page 69

    ... Reduced Media Independent Interface Secure Digital/MultiMediaCard Single Ended Zero Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 70

    ... LPC2460_1 20080123 LPC2420_60_3 Preliminary data sheet Data sheet status Preliminary data sheet 1, Table 2, added LPC2420FBD208. Table 11 “Dynamic characteristics: Static external memory Table 12, dynamic external memory interface characteristics. Figure 10 “External memory read access” 7, updated I and I footnote. OHS ...

  • Page 71

    ... I C-bus — logo is a trademark of NXP B.V. SoftConnect — trademark of NXP B.V. GoodLink — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 20 November 2008 LPC2420/2460 Flashless 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved ...

  • Page 72

    ... Static characteristics . . . . . . . . . . . . . . . . . . . 47 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 53 10.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11 Application information . . . . . . . . . . . . . . . . . 60 11.1 Suggested USB interface solutions . . . . . . . . 60 11.2 Suggested boot memory interface solutions . 65 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 67 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 69 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 70 15 Legal information . . . . . . . . . . . . . . . . . . . . . . 71 Rev. 03 — 20 November 2008 LPC2420/2460 continued >> © NXP B.V. 2008. All rights reserved ...

  • Page 73

    ... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 20 November 2008 Document identifier: LPC2420_60_3 ...