LPC2420_60 NXP Semiconductors, LPC2420_60 Datasheet - Page 68
LPC2420_60
Manufacturer Part Number
LPC2420_60
Description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2420_60.pdf
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13. DAC electrical characteristics
Table 18.
V
14. Application information
LPC2420_60
Product data sheet
Symbol
E
E
E
E
C
R
DDA
Fig 21. Booting from two 8-bit memory chips
Fig 22. Booting from a single 16-bit memory chip
D
L(adj)
O
G
L
L
= 2.7 V to 3.6 V; T
DAC electrical characteristics
Parameter
differential linearity error
integral non-linearity
offset error
gain error
load capacitance
load resistance
14.1 Suggested boot memory interface solutions
A[a_b:1]
amb
‘a_m’ and ‘a_b’ in the following figures refer to the highest order address line of the
memory chip and the highest order microcontroller’s address line used respectively.
CS1
OE
=
D[15:8]
40
BLS1
C to +85
A[a_m:0]
All information provided in this document is subject to legal disclaimers.
IO[7:0]
A[a_b:1]
Conditions
WE
C unless otherwise specified
OE
CE
CS1
WE
OE
Rev. 6.1 — 22 September 2011
D[15:0]
BLS1
BLS0
MEMORY
8-bit
A[a_m:0]
IO[15:0]
WE
OE
CE
UB
LB
MEMORY
16-bit
D[7:0]
BLS0
002aad323
Min
-
-
-
-
-
1
Flashless 16-bit/32-bit microcontroller
A[a_m:0]
IO[7:0]
WE
CE
OE
Typ
1
1.5
0.6
0.6
200
-
LPC2420/2460
MEMORY
8-bit
002aad322
Max
-
-
-
-
-
-
© NXP B.V. 2011. All rights reserved.
Unit
LSB
LSB
%
%
pF
k
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