NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 682
Manufacturer Part Number
Specifications of NH82801GBM SL8YB
Maximum Link Width (MLW) — RO. For the root ports, several values can be taken,
based upon the value of the chipset configuration register field RPC.PC1 (Chipset
Configuration Registers:Offset 0224h:bits1:0) for Ports 1–4 and RPC.PC2 (Chipset
Configuration Registers:Offset 0224h:bits1:0) for Ports 5 and 6.
Maximum Link Speed (MLS) — RO. Set to 1h to indicate the link speed is 2.5 Gb/s.
LCTL—Link Control Register
Address Offset: 50h-51h
Extended Synch (ES) — R/W.
0 = Extended synch disabled.
1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from
L1 prior to entering L0.
Common Clock Configuration (CCC) — R/W.
0 = The Intel
1 = The ICH7 and device are operating with a distributed common reference clock.
Retrain Link (RL) — WO.
0 = This bit always returns 0 when read.
1 = The root port will train its downstream link.
NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5:52, bit 11) to check the status
Link Disable (LD) — R/W.
0 = Link enabled.
1 = The root port will disable the link.
Read Completion Boundary Control (RCBC) — RO. This bit indicates that the read
completion boundary is 64 bytes.
PCI Express* Configuration Registers (Desktop and Mobile Only)
Value of MLW Field
ICH7 and device are not using a common reference clock.
R/W, WO, RO
ICH7 Family Datasheet