XC2VP100-6FF1704I

Manufacturer Part NumberXC2VP100-6FF1704I
DescriptionIC FPGA VIRTEX-II PRO 1704FFBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP100-6FF1704I datasheet
 


Specifications of XC2VP100-6FF1704I

Number Of Logic Elements/cells99216Number Of Labs/clbs11024
Total Ram Bits8183808Number Of I /o1040
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case1704-BBGA, FCBGA
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Gates-
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R
DS083 (v4.7) November 5, 2007
Module 1:
Introduction and Overview
10 pages
Summary of Features
General Description
Architecture
IP Core and Reference Support
Device/Package Combinations and Maximum I/O
Ordering Information
Module 2:
Functional Description
60 pages
Functional Description: RocketIO™ X Multi-Gigabit
Transceiver
Functional Description: RocketIO Multi-Gigabit
Transceiver
Functional Description: Processor Block
Functional Description: PowerPC™ 405 Core
Functional Description: FPGA
-
Input/Output Blocks (IOBs)
-
Digitally Controlled Impedance (DCI)
-
On-Chip Differential Termination
-
Configurable Logic Blocks (CLBs)
-
3-State Buffers
-
CLB/Slice Configurations
-
18-Kb Block SelectRAM™ Resources
-
18-Bit x 18-Bit Multipliers
-
Global Clock Multiplexer Buffers
-
Digital Clock Manager (DCM)
Routing
Configuration
IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision
History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.
© 2002–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v4.7) November 5, 2007
Product Specification
1
Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
0
Module 3:
DC and Switching Characteristics
57 pages
Electrical Characteristics
Performance Characteristics
Switching Characteristics
Pin-to-Pin Output Parameter Guidelines
Pin-to-Pin Input Parameter Guidelines
DCM Timing Parameters
Source-Synchronous Switching Characteristics
Module 4:
Pinout Information
302 pages
Pin Definitions
Pinout Tables
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
Complete Data Sheet
Product Specification
FG256/FGG256 Wire-Bond Fine-Pitch BGA Package
FG456/FGG456 Wire-Bond Fine-Pitch BGA Package
FG676/FGG676 Wire-Bond Fine-Pitch BGA Package
FF672 Flip-Chip Fine-Pitch BGA Package
FF896 Flip-Chip Fine-Pitch BGA Package
FF1148 Flip-Chip Fine-Pitch BGA Package
FF1152 Flip-Chip Fine-Pitch BGA Package
FF1517 Flip-Chip Fine-Pitch BGA Package
FF1696 Flip-Chip Fine-Pitch BGA Package
FF1704 Flip-Chip Fine-Pitch BGA Package
1

XC2VP100-6FF1704I Summary of contents

  • Page 1

    R DS083 (v4.7) November 5, 2007 Module 1: Introduction and Overview 10 pages • Summary of Features • General Description • Architecture • IP Core and Reference Support • Device/Package Combinations and Maximum I/O • Ordering Information Module 2: Functional ...

  • Page 2

    ... XC2VP50 XC2VP70 (4) XC2VPX70 20 2 (3) XC2VP100 Notes speed grade devices are not available in Industrial grade. Logic Cell ≈ (1) 4-input LUT + (1)FF + Carry Logic 2. 3. These devices can be ordered in a configuration without RocketIO transceivers. See 4. Virtex-II Pro X devices equipped with RocketIO X transceiver cores. ...

  • Page 3

    R • Programmable Receiver Equalization • Internal AC Coupling • On-Chip 50Ω Termination - Eliminates the need for external termination resistors • Pre- and Post-Driver Serial and Parallel TX-to-RX RocketIO Transceiver Features (All Except XC2VPX20 and XC2VPX70) • Full-Duplex Serial ...

  • Page 4

    R · HyperTransport (LDT) I/O with current driver buffers · Built-in DDR input and output registers - Proprietary high-performance SelectLink technology for communications between Xilinx devices · High-bandwidth data path · Double Data Rate (DDR) link · Web-based HDL generation ...

  • Page 5

    R Each RocketIO or RocketIO X core implements the following technology: • Serializer and deserializer (SERDES) • Monolithic clock synthesis and clock recovery (CDR) • 10 Gigabit Attachment Unit Interface (XAUI) Fibre Channel (3.1875 Gb/s XAUI), Infiniband, PCI Express, Aurora, ...

  • Page 6

    R • HSTL (1.5V and 1.8V, Class I, II, III, and IV) • SSTL (1.8V and 2.5V, Class I and II) The DCI I/O feature automatically provides on-chip termina- tion for each single-ended I/O standard. The IOB elements also support ...

  • Page 7

    R implemented. In system mode, a Virtex-II Pro device will continue to function while executing non-test Bound- ary-Scan instructions. In test mode, Boundary-Scan test instructions control the I/O pins for testing purposes. The Virtex-II Pro Test Access Port (TAP) supports ...

  • Page 8

    ... Extra SelectIO-Ultra resources occupy available pins in these packages, resulting in a higher user I/O count. These packages are available for the XC2VP40, XC2VP50, and XC2VP100 devices only. The I/Os per package count includes all user I/Os except the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B, ...

  • Page 9

    R Virtex-II Pro Ordering Examples Virtex-II Pro ordering examples are shown in Example: XC2VP40 -7 FF 1152 C Device Type Speed Grade (-5, -6, -7*) *NOTE: -7 devices not available in Industrial grade. Figure 1: Virtex-II Pro Ordering Example, Flip-Chip ...

  • Page 10

    ... Processor Block information added to 1, correct max number of XC2VP30 I/Os to 644. Table 3, add FG676 package option for XC2VP20, XC2VP30, and XC2VP40. XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades -5 and -6, are released to Production status. Table 1: Corrected number of RocketIO transceiver blocks for XC2VP40. ...

  • Page 11

    R Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ...

  • Page 12

    R DS083 (v4.7) November 5, 2007 (1) Virtex-II Pro Array Functional Description RocketIO or RocketIO X DCM Multi-Gigabit Transceiver CLB CLB CLB Configurable Logic SelectIO-Ultra Figure 1: Virtex-II Pro Generic Architecture Overview This module describes the following Virtex™-II ...

  • Page 13

    R Functional Description: RocketIO X Multi-Gigabit Transceiver (MGT) This section summarizes the features of the RocketIO X multi-gigabit transceiver. For an in-depth discussion of the RocketIO X MGT, including digital and analog design con- siderations, refer to the RocketIO X ...

  • Page 14

    R PACKAGE PINS AVCCAUXTX 2.5V VTRX Termination Supply RX RXP RXN Deserializer Manager TXP Serializer TXN GNDA TX/RX GND AVCCAUXRX 1.5V VTTX Termination Supply TX DS083 (v4.7) November 5, 2007 Product Specification Virtex-II Pro and Virtex-II Pro X Platform FPGAs: ...

  • Page 15

    R Output Swing and Emphasis The output swing and emphasis levels are fully programma- ble. Each is controlled via attributes at configuration, and can be modified via the PMA attribute programming bus. The programmable output swing control can adjust the ...

  • Page 16

    R RXP and RXN as shown in Figure 5. This supports multiple termination styles, including high-side, low-side, and differ- ential (floating or active). This configuration supports receiver termination compatible to Virtex-II Pro devices, VTRX RXP RXN PCS Fabric Data Interface ...

  • Page 17

    R Disparity Control The 8B/10B encoder is initialized with a negative running disparity. Unique control allows forcing the current running disparity state. TXRUNDISP signals its current running disparity. This may be useful in those cases where there is a need ...

  • Page 18

    R cation is given at the receiver interface. The realignment indicator is a distinct output. The transceiver continuously monitors the data for the pres- ence of the 10-bit character(s). Upon each occurrence of a 10-bit character, the data is checked ...

  • Page 19

    R ing character, and remembers its location in the buffer. At some point, one transceiver designated as the master instructs all the transceivers to align to the channel bonding character "P" (or to some location relative to the channel bonding ...

  • Page 20

    R Other RocketIO X Features and Notes Loopback In order to facilitate testing without having the need to either apply patterns or measure data at GHz rates, four program- mable loop-back features are available. The first option, serial loopback, is ...

  • Page 21

    R Functional Description: RocketIO Multi-Gigabit Transceiver (MGT) This section summarizes the features of the RocketIO multi-gigabit transceiver. For an in-depth discussion of the RocketIO MGT, including digital and analog design consid- erations, refer to the RocketIO Transceiver User RocketIO Overview ...

  • Page 22

    R PACKAGE PINS AVCCAUXRX 2.5V RX VTRX Termination Supply RX RXP RXN Deserializer Manager TXP Serializer TXN GNDA TX/RX GND AVCCAUXTX 2.5V TX VTTX Termination Supply TX Output Swing and Pre-emphasis The output swing and pre-emphasis levels of the RocketIO ...

  • Page 23

    R Serializer The serializer multiplies the reference frequency provided on REFCLK by 20. The multiplication of the clock is achieved by using an embedded PLL. Data is converted from parallel to serial format and transmit- ted on the TXP and ...

  • Page 24

    R Table 5: Clock Ratios for Various Data Widths Frequency Ratio of Fabric Data Width USRCLK:USRCLK2 1-byte 1:2 2-byte 1:1 4-byte 2:1 Notes: 1. Each edge of slower clock must align with falling edge of faster clock. FPGA Transmit Interface ...

  • Page 25

    R Receiver Buffer The receiver includes buffers (FIFOs) in the datapath. This section gives the reasons for including the buffers and out- lines their operation. The receiver buffer is required for two reasons: • Clock correction to accommodate the slight ...

  • Page 26

    R The top half of the figure shows the transmission of words split across four transceivers (channels or lanes). PPPP, QQQQ, RRRR, SSSS, and TTTT represent words sent over the four channels. The bottom-left portion of Figure 13 tion in ...

  • Page 27

    R CRC may adjust certain trailing bytes to generate the required running disparity at the end of the packet. On the receiver side, the CRC logic verifies the received CRC value, supporting the same standards as above. The CRC logic ...

  • Page 28

    R RocketIO and RocketIO X Feature Comparison Table 7 summarizes the major differences between the RocketIO and RocketIO X MGTs. The User Guide has more details, including a design migration guide in the Appendix. Table 7: RocketIO PMA versus RocketIO ...

  • Page 29

    R Functional Description: Processor Block This section briefly describes the interfaces and compo- nents of the Processor Block. The subsequent section, Functional Description: Embedded PowerPC 405 Core beginning on page 20, offers a summary of major PPC405 core features. For ...

  • Page 30

    R • Single-cycle and multi-cycle mode option for I-side and D-side interfaces • Single cycle = one CPU clock cycle; multi-cycle = minimum of two and maximum of eight CPU clock cycles • FPGA configurable DCR addresses within DSOCM and ...

  • Page 31

    R The Trace port provides instruction execution trace informa- tion to an external trace tool. The PPC405 core is capable of back trace and forward trace. Back trace is the tracing of instructions prior to a debug event while forward ...

  • Page 32

    R • Execution unit • Timers • Debug logic unit It operates on instructions in a five stage pipeline consisting of a fetch, decode, execute, write-back, and load write-back stage. Most instructions execute in a single cycle, including loads and ...

  • Page 33

    R memory protection. Working with appropriate system-level software, the MMU provides the following functions: • Translation of the 4 GB effective address space into physical addresses • Independent enabling of instruction and data translation/protection • Page-level access control using the ...

  • Page 34

    R Time Base (Incrementer) TBL (32 bits) External 0 31 Clock Source 29 Bit Bit Bit Bit Bit 11 (2 clocks) 17 Bit 15 (2 clocks) 13 Bit ...

  • Page 35

    R Functional Description: FPGA Input/Output Blocks (IOBs) Virtex-II Pro I/O blocks (IOBs) are provided in groups of two or four on the perimeter of each device. Each IOB can be used as input and/or output for single-ended I/Os. Two IOBs ...

  • Page 36

    R Table 9: Supported Differential Signal I/O Standards Output Input I/O Standard V V CCO CCO LDT_25 2.5 N/R LVDS_25 2.5 N/R LVDSEXT_25 2.5 N/R BLVDS_25 2.5 N/R ULVDS_25 2.5 N/R LVPECL_25 2.5 N/R (1) LDT_25_DT 2.5 2.5 (1) LVDS_25_DT ...

  • Page 37

    R DCM 0° CLK1 D2 Q2 CLK2 This DDR mechanism can be used to mirror a copy of the clock on the output. This is useful for propagating a clock along the data that has an identical delay. ...

  • Page 38

    R (O/T) 1 (O/T) CE (O/T) CLK1 SR Shared by all registers REV (O/T) CLK2 (O/T) 2 Figure 21: Register / Latch Configuration in an IOB Block V CCO Clamp OBUF Diode V CCO Program Current V CCO Program Delay ...

  • Page 39

    R Table 11: LVCMOS Programmable Currents (Sink and Source) SelectIO-Ultra LVTTL 2 mA LVCMOS33 2 mA LVCMOS25 2 mA LVCMOS18 2 mA LVCMOS15 2 mA Figure 23 shows the SSTL2, SSTL18, and HSTL configura- tions. HSTL can sink current up ...

  • Page 40

    R Bank 0 Bank 1 Bank 5 Bank 4 Figure 24: I/O Banks: Wire-Bond Packages (FG) Top View Bank 1 Bank 0 Bank 4 Bank 5 Figure 25: I/O Banks: Flip-Chip Packages (FF) Top View Some input standards require a ...

  • Page 41

    R Table 12: Summary of Voltage Supply Requirements for All Input and Output Standards V CCO I/O Standard Output Input (1) LVTTL (1) LVCMOS33 (1) LVDCI_33 3.3 3.3 (2) PCIX (2) PCI33_3 (2) PCI66_3 LVDS_25 LVDSEXT_25 LDT_25 ULVDS_25 Note (3) ...

  • Page 42

    R Digitally Controlled Impedance (DCI) Today’s chip output signals with fast edge rates require ter- mination to prevent reflections and maintain signal integrity. High pin count packages (especially ball grid arrays) can not accommodate external termination resistors. Virtex-II Pro XCITE ...

  • Page 43

    R Table 15: SelectIO-Ultra Differential Buffers With On-Chip Termination I/O Standard Description LVDS 2.5V LVDS Extended 2.5V Figure 28 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O standards. For a complete list, see the HSTL_I ...

  • Page 44

    R Figure 29 provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL18_I_DCI, and SSTL18_II_DCI I/O standards. For a complete list, see the Conventional DCI Transmit Conventional Receive Conventional Transmit DCI Receive DCI Transmit DCI Receive Bidirectional Reference Resistor Recommended ...

  • Page 45

    R Figure 30 provides examples illustrating the use of the LVDS_25_DCI and LVDSEXT_25_DCI I/O standards. For a complete list, see the Virtex-II Pro Platform FPGA User . Guide LVDS_25_DCI and LVDSEXT_25_DCI Receiver Z 0 Conventional Conventional ...

  • Page 46

    R Configurable Logic Blocks (CLBs) The Virtex-II Pro configurable logic blocks (CLB) are orga- nized in an array and are used to build combinatorial and synchronous logic designs. Each CLB element is tied to a switch matrix to access the ...

  • Page 47

    R SHIFTIN SOPIN WG4 WG3 WG2 WG1 ALTDIG BY SLICEWE[2:0] CE CLK SR DS083 (v4.7) November 5, 2007 Product Specification Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description COUT 0 Dual-Port Shift-Reg MUXCY 1 ...

  • Page 48

    REV CLK SR REV SR BX Figure 35: Register / Latch Configuration in a Slice The set and reset functionality of a register or a latch can be ...

  • Page 49

    R Figure 36, Figure 37, and Figure 38 ple configurations. RAM 16x1S RAM 4 D A[3:0] A[4:1] 4 WG[4: (BY) D WSG (SR WCLK CK Figure 36: Distributed SelectRAM+ (RAM16x1S) RAM 32x1S (BX) A[4] RAM 4 ...

  • Page 50

    R Shift Registers Each function generator can also be configured as a 16-bit shift register. The write operation is synchronous with a clock input (CLK) and an optional clock enable, as shown in Figure 39. A dynamic read access is ...

  • Page 51

    R Multiplexers Virtex-II Pro function generators and associated multiplex- ers can implement the following: • 4:1 multiplexer in one slice • 8:1 multiplexer in two slices • 16:1 multiplexer in one CLB element (4 slices) • 32:1 multiplexer in two ...

  • Page 52

    R COUT the next CLB (First Carry Chain LUT O I LUT CIN COUT O I LUT O I LUT CIN DS083 (v4.7) November 5, 2007 Product Specification Virtex-II Pro and Virtex-II Pro X Platform ...

  • Page 53

    R Sum of Products Each Virtex-II Pro slice has a dedicated OR gate named ORCY, ORing together outputs from the slices carryout and the ORCY from an adjacent slice. The ORCY gate with the dedicated Sum of Products (SOP) chain ...

  • Page 54

    ... Device Slice S3 XC2VP2 Slice XC2VP4 S2 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 DS031_37_060700 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 Programmable Switch connection matrix CLB-II www.xilinx.com Figure 46. The switch matrices corresponding to shows the number of 3-state buffers available in 3-State Buffers Total Number per Row of 3-State Buffers 44 44 ...

  • Page 55

    ... XC2VP50 23,616 XC2VP70 104 x 82 33,088 XC2VPX70 104 x 82 33,088 XC2VP100 120 x 94 44,096 Notes: 1. The carry-chains and SOP chains can be split or cascaded Block SelectRAM+ Resources Introduction Virtex-II Pro devices incorporate large amounts block SelectRAM+ resources. These complement the dis- tributed SelectRAM+ resources that provide shallow RAM structures implemented in CLBs ...

  • Page 56

    R nally in user logic. In such cases, the width is viewed These extra parity bits are stored and behave exactly as the other bits, including the timing parameters. ...

  • Page 57

    R Each block SelectRAM+ cell is a fully synchronous memory, as illustrated in Figure 48. The two ports have independent inputs and outputs and are independently clocked. 18-Kbit Block SelectRAM DIA DIPA ADDRA WEA ENA SSRA CLKA DIB DIPB ADDRB ...

  • Page 58

    ... No change during write XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VPX20 XC2VP40 New XC2VP50 XC2VP70 DS083-2_12_050901 XC2VPX70 XC2VP100 Figure 52 Table 24. All con- XC2VP4 device. Figure 52: XC2VP4 Block RAM Column Layout www.xilinx.com shows the number of columns as well as the total Total SelectRAM+ Memory Columns Blocks ...

  • Page 59

    ... XC2VPX20 XC2VP40 DS031_33_101000 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 In addition to the built-in multiplier blocks, the CLB elements have dedicated logic to implement efficient multipliers in logic. (Refer to Global Clock Multiplexer Buffers Virtex-II Pro devices have 16 clock input pins that can also be used as regular user I/Os. Eight clock pads center on ...

  • Page 60

    R 8 clock pads Virtex-II Pro Device 8 clock pads Figure 55: Virtex-II Pro Clock Pads Figure 56: Virtex-II Pro Clock Multiplexer Buffer Configuration DS083 (v4.7) November 5, 2007 Product Specification Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional ...

  • Page 61

    R Figure 57 shows clock distribution in Virtex-II Pro devices. In each quadrant eight clocks are organized in clock rows. A clock row supports CLB rows (eight up and eight down). To reduce power consumption, ...

  • Page 62

    R BUFGMUX DS083-2_63_121701 Figure 60: Virtex-II Pro BUFGMUX Function If the presently selected clock is Low while S changes goes Low after S has changed, the output is kept Low until ...

  • Page 63

    R The DCM has the following general control signals: • RST input pin: resets the entire DCM • LOCKED output pin: asserted High when all enabled DCM circuits have locked. • STATUS output pins (active High): shown in Table 27: ...

  • Page 64

    R CLKIN CLKOUT_PHASE_SHIFT CLKFB = NONE CLKIN CLKOUT_PHASE_SHIFT CLKFB = FIXED CLKIN CLKOUT_PHASE_SHIFT = VARIABLE CLKFB Two separate components of the phase shift range must be understood: • attribute range PHASE_SHIFT • DCM timing parameter range FINE_SHIFT_RANGE The attribute is ...

  • Page 65

    ... XC2VPX20 8 XC2VP30 8 XC2VP40 10 XC2VP50 12 XC2VP70 14 XC2VPX70 14 XC2VP100 16 24 Horizontal Long Lines 24 Vertical Long Lines 120 Horizontal Hex Lines 120 Vertical Hex Lines 40 Horizontal Double Lines 40 Vertical Double Lines 16 Direct Connections (total in all four directions) 8 Fast Connects DS083 (v4.7) November 5, 2007 Product Specification ...

  • Page 66

    R • The double lines route signals to every first or second block away in all four directions. Organized in a staggered pattern, double lines can be driven only at their endpoints. Double-line signals can be accessed either at the ...

  • Page 67

    R Configuration Virtex-II Pro devices are configured by loading application specific configuration data into the internal configuration memory. Configuration is carried out using a subset of the device pins, some of which are dedicated, while others can be re-used as ...

  • Page 68

    ... XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 Configuration Sequence The configuration of Virtex-II Pro devices is a three-phase process. First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is activated by a start-up process. DS083 (v4.7) November 5, 2007 ...

  • Page 69

    R synchronously. The sequence can also be paused at any stage, until lock has been achieved on any or all DCMs, as well as DCI. Readback In this mode, configuration data from the Virtex-II Pro FPGA device can be read ...

  • Page 70

    ... DOUT. Table 8, page 24 and Table 10, page from 1.08V to 1.1V. XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades -5 and -6, are released to Production status. Section BUFGMUX, page 50: Corrected the definition of the "presently selected clock" I1. Corrected signal names in CLK1 to I0 and I1 ...

  • Page 71

    R Date Version 10/10/05 4.5 • 03/05/07 4.6 No changes in Module 2 for this revision. • Updated copyright notice and legal disclaimer. 11/05/07 4.7 • Debug Interface, page Updated IEEE 1149.1 compliance statement. Notice of Disclaimer THE XILINX HARDWARE ...

  • Page 72

    R DS083 (v4.7) November 5, 2007 (1) Virtex-II Pro Electrical Characteristics Virtex™-II Pro devices are provided in -7, -6, and -5 speed grades, with -7 having the highest performance. Virtex-II Pro DC and AC characteristics are specified for ...

  • Page 73

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 2: Recommended Operating Conditions Symbol Internal supply voltage relative to GND CCINT Internal supply voltage relative to GND, T +100°C Auxiliary supply voltage relative ...

  • Page 74

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Data retention V CCINT V DRINT (below which configuration data might be lost) Data retention V CCAUX V ...

  • Page 75

    ... XC2VP70 85 1700 mA XC2VPX70 85 1700 mA XC2VP100 100 2200 mA XC2VP2 1.0 8.0 mA XC2VP4 1.0 8.0 mA XC2VP7 1.0 8.0 mA XC2VP20 1. XC2VPX20 1. XC2VP30 1. XC2VP40 1. XC2VP50 1 XC2VP70 1 XC2VPX70 1 XC2VP100 1. XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 20 100 mA XC2VP70 20 100 mA XC2VPX70 20 100 mA XC2VP100 20 125 mA Module ...

  • Page 76

    ... V and V can power on at any ramp rate. Power CCAUX CCO supplies can be turned on in any sequence. Table 5: Power-On Current for Virtex-II Pro Devices Symbol XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 I 500 500 500 CCINTMIN I 250 250 ...

  • Page 77

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics SelectIO-Ultra DC Input and Output Levels Values for V and V are recommended input voltages Values for I and I are guaranteed over the recom- ...

  • Page 78

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics LVDS DC Specifications (LVDS_25) Table 8: LVDS DC Specifications DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q ...

  • Page 79

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics RocketIO DC Input and Output Levels Table 11: RocketIO X Input/Output Voltage Specifications Parameter Peak-to-Peak Differential Input Voltage (2,3) Single-Ended Output Voltage Swing Peak-to-Peak Differential Output Voltage ...

  • Page 80

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Virtex-II Pro Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Virtex-II Pro devices. The numbers reported here are fully ...

  • Page 81

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 14 shows internal (register-to-register) performance. Values are reported in MHz. Table 14: Register-to-Register Performance Description Basic Functions: 16-bit Address Decoder 32-bit Address Decoder 64-bit Address Decoder ...

  • Page 82

    ... XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 Testing of Switching Characteristics All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test pat- terns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, ...

  • Page 83

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 17: Processor Block Switching Characteristics Description Setup and Hold Relative to Clock (CPMC405CLOCK) Device Control Register Bus control inputs Device Control Register Bus data inputs Clock ...

  • Page 84

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 19: Processor Block JTAG Switching Characteristics Description Setup and Hold Relative to Clock (JTAGC405TCK) JTAG control inputs JTAG reset input Clock to Out JTAG control outputs ...

  • Page 85

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics RocketIO Switching Characteristics Table 22: RocketIO X Reference Clock Switching Characteristics Description (1) Reference Clock frequency range Reference Clock frequency tolerance Reference Clock rise time Reference Clock ...

  • Page 86

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 24: RocketIO X Receiver Switching Characteristics Description Receive total jitter tolerance using default equalization and PRBS-15 pattern Receive random jitter tolerance Receive sinusoidal jitter tolerance measured ...

  • Page 87

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 25: RocketIO Receiver Switching Characteristics Description Receive total jitter tolerance Receive deterministic jitter tolerance (3) Receive latency RXUSRCLK duty cycle RXUSRCLK2 duty cycle Notes ...

  • Page 88

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 26: RocketIO X Transmitter Switching Characteristics Description Serial data rate (3) Serial data output total jitter (p-p) Serial data output deterministic jitter (p-p) (3,4) Serial data ...

  • Page 89

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 27: RocketIO Transmitter Switching Characteristics Description Serial data rate, full-speed clock (3) Serial data rate, half-speed clock (2X oversampling) Serial data output deterministic jitter Serial data ...

  • Page 90

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 28: RocketIO X Fabric Interface Characteristics Description TX/RXUSRCLK frequency TX/RXUSRCLK2 frequency Table 29: RocketIO RXUSRCLK Switching Characteristics Description Setup and Hold Relative to Clock (RXUSRCLK) CHBONDI ...

  • Page 91

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 30: RocketIO RXUSRCLK2 Switching Characteristics (Continued) Description Clock RXUSRCLK2 minimum pulse width, High RXUSRCLK2 minimum pulse width, Low Table 31: RocketIO TXUSRCLK2 Switching Characteristics Description Setup ...

  • Page 92

    ... XC2VP2 2.30 IOPLID XC2VP4 2.57 XC2VP7 2.50 XC2VP20 2.65 XC2VPX20 2.65 XC2VP30 2.69 XC2VP40 3.30 XC2VP50 3.86 XC2VP70 4.00 XC2VPX70 4.00 XC2VP100 N/A T All 0.60 IOCKIQ www.xilinx.com Speed Grade -6 -5 Units 0.87 0.91 ns, max 1.94 2.06 ns, max 1.94 2.06 ns, max 1.94 2 ...

  • Page 93

    ... XC2VP7 2.48/–2.05 XC2VP20 2.63/–2.05 XC2VPX20 2.63/–2.05 XC2VP30 2.67/–2.07 XC2VP40 3.28/–2.56 XC2VP50 3.84/–3.02 XC2VP70 3.98/–3.13 XC2VPX70 3.98/–3.13 XC2VP100 T /T All 0.39/ 0.01 IOICECK IOCKICE T All IOSRCKI T All IOSRIQ T All GSRQ Table www.xilinx.com ...

  • Page 94

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics IOB Input Switching Characteristics Standard Adjustments Table 33 gives all standard-specific data input delay adjustments. Table 33: IOB Input Switching Characteristics Standard Adjustments Description LVTTL (Low-Voltage Transistor-Transistor ...

  • Page 95

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 33: IOB Input Switching Characteristics Standard Adjustments (Continued) Description HSLVDCI, 1.8V HSLVDCI, 2.5V HSLVDCI, 3.3V GTL (Gunning Transceiver Logic) with DCI GTL Plus with DCI HSTL ...

  • Page 96

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVCMOS25 with 12 mA drive and fast slew rate. For other standards, adjust the ...

  • Page 97

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics IOB Output Switching Characteristics Standard Adjustments Table 35 gives all standard-specific adjustments for output delays terminating at pads, based on standard capacitive load Output delays ...

  • Page 98

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 35: IOB Output Switching Characteristics Standard Adjustments (Continued) Description LVCMOS, 2.5V, Fast LVCMOS, 2.5V, Fast LVCMOS, 2.5V, Fast LVCMOS, 2.5V, ...

  • Page 99

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 35: IOB Output Switching Characteristics Standard Adjustments (Continued) Description HSTL, Class II HSTL, Class III HSTL, Class IV HSTL, Class I, 1.8V HSTL, Class II, 1.8V ...

  • Page 100

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 36 shows the test setup parameters used for measuring Input standard adjustments (see Table 36: Input Delay Measurement ...

  • Page 101

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Output Delay Measurements Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used ...

  • Page 102

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 37: Output Delay Measurement Methodology Description SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V ...

  • Page 103

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Clock Distribution Switching Characteristics Table 38: Clock Distribution Switching Characteristics Description Global Clock Buffer I input to O output Global Clock Buffer S input Setup/Hold to I1 ...

  • Page 104

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics CLB Distributed RAM Switching Characteristics Table 40: CLB Distributed RAM Switching Characteristics Description Sequential Delays Clock CLK to X/Y outputs (WE active mode ...

  • Page 105

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Multiplier Switching Characteristics Table 42: Multiplier Switching Characteristics Description Propagation Delay to Output Pin Input to Pin35 Input to Pin34 Input to Pin33 Input to Pin32 Input ...

  • Page 106

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Table 43: Pipelined Multiplier Switching Characteristics Description Setup and Hold Times Before/After Clock Data Inputs Clock Enable Reset Clock to Output Pin Clock to Pin35 Clock to ...

  • Page 107

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Block SelectRAM+ Switching Characteristics Table 44: Block SelectRAM+ Switching Characteristics Description Sequential Delays Clock CLK to DOUT output Setup and Hold Times Before Clock CLK ADDR inputs ...

  • Page 108

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Configuration Timing Configuration Memory Clearing Parameters Power-up timing of configuration signals is shown PROG_B INIT_B CCLK (Output or Input) M0, M1, M2* (Required) Table ...

  • Page 109

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Master/Slave Serial Mode Parameters Clock timing for Slave Serial configuration programming is shown in Figure 9. Programming parameters for both Slave and Master modes are given in ...

  • Page 110

    ... T 1 SMCCD SMDCC 7 T SMCKBY No Write Write Figure Device References XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 1/2 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 3/4 5/6 7 www.xilinx.com 4 T SMCCCS 6 T SMWCC No Write Write ds083-3_10_012004 Symbol Value 5.0/0.0 5.0/0.0 5.0/0.0 5.0/0.0 5.0/0 5.0/0.0 SMDCC SMCCD 5 ...

  • Page 111

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics JTAG Test Access Port Switching Characteristics Characterization data for some of the most commonly requested timing parameters shown in FI TMS TDI TCK TDO Data to be ...

  • Page 112

    ... DCM output jitter is already included in the timing calculation. DS083 (v4.7) November 5, 2007 Product Specification Symbol Device T XC2VP2 ICKOFDCM XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 threshold with test setup shown in Figure CC www.xilinx.com Speed Grade - 1.55 1.59 1.62 1.58 1.61 1.65 1.63 1.68 1 ...

  • Page 113

    ... DCM output jitter is already included in the timing calculation. DS083 (v4.7) November 5, 2007 Product Specification Symbol Device T XC2VP2 ICKOF XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 threshold with test setup shown in Figure CC www.xilinx.com Speed Grade - 3.19 3.52 3.82 3.39 3.91 4.27 3.59 4.00 4 ...

  • Page 114

    ... XC2VP20 1.68/–0.53 XC2VPX20 1.68/–0.53 XC2VP30 1.81/–0.74 XC2VP40 1.85/–0.65 XC2VP50 1.85/–0.57 XC2VP70 1.86/–0.45 XC2VPX70 1.86/–0.45 XC2VP100 . DCD_CLK180 www.xilinx.com Speed Grade - 1.54/–0.57 1.54/–0.56 1.59/–0.58 1.59/–0.57 1.66/–0.59 1.66/–0.57 1.68/–0.53 1.68/– ...

  • Page 115

    ... XC2VP20 1.76/–0.24 XC2VPX20 1.76/–0.24 XC2VP30 1.75/–0.22 XC2VP40 2.25/–0.54 XC2VP50 2.93/–1.02 XC2VP70 2.79/–0.72 XC2VPX70 2.79/–0.72 XC2VP100 N/A www.xilinx.com Speed Grade -5 Units -6 ns 1.85/–0.41 1.96/–0.43 1.83/–0.31 1.90/–0.29 ns 1.81/–0.24 1.88/–0.19 ns 1.83/– ...

  • Page 116

    ... CLK2X and CLK2X180 may not be used as the input to the CLKFB pin. See the information. 6. For the XC2VP100 -6 device only, clock macros for corner DCMS (X0Y0, X5Y0, X0Y1, X5Y1) are required to operate at maximum clock frequency. See XAPP685 for implementation examples. ...

  • Page 117

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Input Clock Tolerances Table 55: Input Clock Tolerances Description Input Clock Low/High Pulse Width PSCLK PSCLK_PULSE PSCLK_PULSE and (3) PSCLK and CLKIN CLKIN_PULSE Input Clock Cycle-Cycle Jitter ...

  • Page 118

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Output Clock Jitter Table 56: Output Clock Jitter Description Clock Synthesis Period Jitter CLK0 CLK90 CLK180 CLK270 CLK2X, CLK2X180 CLKDV (integer division) CLKDV (non-integer division) CLKFX, CLKFX180 ...

  • Page 119

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Miscellaneous Timing Parameters Table 58: Miscellaneous Timing Parameters Description Time Required to Achieve LOCK (1) Using DLL outputs Using CLKFX outputs Additional lock time with fine phase ...

  • Page 120

    ... DS083 (v4.7) November 5, 2007 Product Specification Symbol Device T DCD_LOCAL All T DCD_CLK180 T XC2VP2 CKSKEW XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 www.xilinx.com Speed Grade – – – 0.10 0.10 0.20 0.10 0.11 0.13 0.13 0.13 0.13 0.13 0.13 0.13 ...

  • Page 121

    ... DS083 (v4.7) November 5, 2007 Product Specification Symbol Device/Package T XC2VP2FF672 PKGSKEW XC2VP4FF672 XC2VP7FF672 XC2VP7FF896 XC2VP20FF896 XC2VPX20FF896 XC2VP20FF1152 XC2VP30FF896 XC2VP30FF1152 XC2VP40FF1152 XC2VP40FF1148 XC2VP50FF1152 XC2VP50FF1148 XC2VP50FF1517 XC2VP70FF1517 XC2VP70FF1704 XC2VPX70FF1704 XC2VP100FF1704 XC2VP100FF1696 Symbol Device T All SAMP DCD_CLK180 www.xilinx.com Value Units 104 102 92 101 93 93 106 86 112 92 100 88 101 97 ...

  • Page 122

    ... PHDCM_0 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100 DCD_CLK180 Notes: 1. Jitter values and accumulation methodology to be provided in sec- a future release of this document. The absolute period jitter values found in the particular DCM output clock used to clock the IOB FF can be used for a best case analysis. ...

  • Page 123

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Virtex-II Pro Receiver Data-Valid Window ( the required minimum aggregate valid data period for X a source-synchronous data bus at the pins of the device ...

  • Page 124

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Date Version 12/03/02 2.5 Updated parametric information in: • • • • • 01/20/03 2.6 Updated parametric information in: • • • • 03/24/03 2.7 • • ...

  • Page 125

    ... XAPP659 . Table 4: Removed MIN column from table. XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades -5 and -6, updated and released to Production status as per speedsfile v1.83. Featured changes: - Speedsfile parameter values for -7 speed grade added for devices XC2VP2-XC2VP70. ...

  • Page 126

    ... Characteristics: Added parameter F Table 48, SelectMAP Mode Write Timing DATA[0:7] setup/hold time, by device, and added new parameter specifications for XC2VP70 and XC2VP100 devices. Table 54, Operating Frequency Ranges: Added callouts for existing Footnote (3) to the four CLKIN parameters. Added new Footnote (4) to the four CLKIN parameters. Added new Footnote (5) to CLK2X, CLK2X180. Added new Footnote (6) to CLK2X, CLK2X180 ...

  • Page 127

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Date Version 11/17/04 4.1 • • • • • • • 03/01/05 4.2 • • • • • • • • • • • • • • ...

  • Page 128

    R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics Date Version 09/15/05 4.4 • • • • • • • 10/10/05 4.5 • • 03/05/07 4.6 No changes in Module 3 for this revision. 11/05/07 4.7 ...

  • Page 129

    R 2 DS083 (v4.7) November 5, 2007 This document provides Virtex™-II Pro Device/Package Combinations, Maximum I/Os, and Virtex-II Pro Pin Defini- tions, followed by pinout tables, for these packages: • FG256/FGG256 Fine-Pitch BGA Package • FG456/FGG456 Fine-Pitch BGA ...

  • Page 130

    R Table 3: Virtex-II Pro Available I/Os and RocketIO MGT Pins per Device/Package Combination User I/Os & Virtex-II Pro RocketIO FG256/ Device MGT Pins FGG256 Available User 140 I/Os RocketIO XC2VP2 36 MGT Pins Differential I/O 68 Pairs Available User ...

  • Page 131

    ... User I/Os RocketIO X XC2VPX70 MGT Pins Differential I/O Pairs Available User I/Os RocketIO XC2VP100 MGT Pins Differential I/O Pairs Notes: 1. Wire-bond packages include FGGnnn Pb-free versions. See DS083 (v4.7) November 5, 2007 Product Specification Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information ...

  • Page 132

    R Virtex-II Pro Pin Definitions This section describes the pinouts for Virtex-II Pro devices in the following packages: • FG256/FGG256, FG456/FGG456, and FG676/FGG676: wire-bond fine-pitch BGA of 1.00 mm pitch • FF672, FF896, FF1148, FF1152, FF1517, FF1696, and FF1704: flip-chip ...

  • Page 133

    R Table 4: Virtex-II Pro Pin Definitions (Continued) Pin Name Direction GCLKx (S/P) Input/Output VRP Input VRN Input V Input REF (1) Dedicated Pins: CCLK Input/Output PROG_B Input DONE Input/Output M2, M1, M0 Input HSWAP_EN Input TCK Input TDI Input ...

  • Page 134

    R Table 4: Virtex-II Pro Pin Definitions (Continued) Pin Name Direction BREFCLKN, Input (2) BREFCLKP VTRXPAD# Input VTTXPAD# Input GNDA# Input RXPPAD# Input RXNPAD# Input TXPPAD# Output TXNPAD# Output Notes: 1. All dedicated pins (JTAG and configuration) are powered by ...

  • Page 135

    R FG256/FGG256 Fine-Pitch BGA Package As shown in Table 5, XC2VP2 and XC2VP4 Virtex-II Pro devices are available in the FG256/FGG256 fine-pitch BGA package. The pins in each of these devices are identical. Following this table are the Package Specifications ...

  • Page 136

    R Table 5: FG256/FGG256 — XC2VP2 and XC2VP4 Bank ...

  • Page 137

    R Table 5: FG256/FGG256 — XC2VP2 and XC2VP4 Bank ...

  • Page 138

    R Table 5: FG256/FGG256 — XC2VP2 and XC2VP4 Bank ...

  • Page 139

    R Table 5: FG256/FGG256 — XC2VP2 and XC2VP4 Bank ...

  • Page 140

    R Table 5: FG256/FGG256 — XC2VP2 and XC2VP4 Bank 7 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ...

  • Page 141

    R Table 5: FG256/FGG256 — XC2VP2 and XC2VP4 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ...

  • Page 142

    R Table 5: FG256/FGG256 — XC2VP2 and XC2VP4 Bank N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Notes: 1. See Table 4 for ...

  • Page 143

    R FG256/FGG256 Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 1: FG256/FGG256 Fine-Pitch BGA Package Specifications DS083 (v4.7) November 5, 2007 Product Specification Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information www.xilinx.com Module ...

  • Page 144

    R FG456/FGG456 Fine-Pitch BGA Package As shown in Table 6, XC2VP2, XC2VP4, and XC2VP7 Virtex-II Pro devices are available in the FG456/FGG456 fine-pitch BGA package. The pins in these devices are same, except for the differences shown in the "No ...

  • Page 145

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 1 IO_L07P_1 1 IO_L06N_1 1 IO_L06P_1 1 IO_L05_1/No_Pair 1 IO_L03N_1/VREF_1 1 IO_L03P_1 1 IO_L02N_1 1 IO_L02P_1 1 IO_L01N_1/VRP_1 1 IO_L01P_1/VRN_1 2 IO_L01N_2/VRP_2 2 IO_L01P_2/VRN_2 2 IO_L02N_2 2 IO_L02P_2 ...

  • Page 146

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 2 IO_L56N_2 2 IO_L56P_2 2 IO_L58N_2/VREF_2 2 IO_L58P_2 2 IO_L60N_2 2 IO_L60P_2 2 IO_L85N_2 2 IO_L85P_2 2 IO_L86N_2 2 IO_L86P_2 2 IO_L88N_2/VREF_2 2 IO_L88P_2 2 IO_L90N_2 2 IO_L90P_2 ...

  • Page 147

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 3 IO_L49N_3 3 IO_L49P_3 3 IO_L48N_3 3 IO_L48P_3 3 IO_L47N_3 3 IO_L47P_3 3 IO_L45N_3/VREF_3 3 IO_L45P_3 3 IO_L43N_3 3 IO_L43P_3 3 IO_L06N_3 3 IO_L06P_3 3 IO_L05N_3 3 IO_L05P_3 ...

  • Page 148

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 4 IO_L69P_4/VREF_4 4 IO_L74N_4/GCLK3S 4 IO_L74P_4/GCLK2P 4 IO_L75N_4/GCLK1S 4 IO_L75P_4/GCLK0P 5 IO_L75N_5/GCLK7S 5 IO_L75P_5/GCLK6P 5 IO_L74N_5/GCLK5S 5 IO_L74P_5/GCLK4P 5 IO_L69N_5/VREF_5 5 IO_L69P_5 5 IO_L67N_5 5 IO_L67P_5 5 IO_L09N_5/VREF_5 ...

  • Page 149

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 6 IO_L06N_6 6 IO_L43P_6 6 IO_L43N_6 6 IO_L45P_6 6 IO_L45N_6/VREF_6 6 IO_L47P_6 6 IO_L47N_6 6 IO_L48P_6 6 IO_L48N_6 6 IO_L49P_6 6 IO_L49N_6 6 IO_L51P_6 6 IO_L51N_6/VREF_6 6 IO_L53P_6 ...

  • Page 150

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 7 IO_L88N_7/VREF_7 7 IO_L86P_7 7 IO_L86N_7 7 IO_L85P_7 7 IO_L85N_7 7 IO_L60P_7 7 IO_L60N_7 7 IO_L58P_7 7 IO_L58N_7/VREF_7 7 IO_L56P_7 7 IO_L56N_7 7 IO_L55P_7 7 IO_L55N_7 7 IO_L54P_7 ...

  • Page 151

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 ...

  • Page 152

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 7 VCCO_7 7 VCCO_7 7 VCCO_7 7 VCCO_7 N/A CCLK N/A PROG_B N/A DONE N/A M0 N/A M1 N/A M2 N/A TCK N/A TDI N/A TDO N/A TMS ...

  • Page 153

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description N/A VTRXPAD6 N/A AVCCAUXRX6 N/A AVCCAUXTX7 N/A VTTXPAD7 N/A TXNPAD7 N/A TXPPAD7 N/A GNDA7 N/A RXPPAD7 N/A RXNPAD7 N/A VTRXPAD7 N/A AVCCAUXRX7 N/A AVCCAUXTX9 N/A VTTXPAD9 N/A TXNPAD9 ...

  • Page 154

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description N/A AVCCAUXTX18 N/A AVCCAUXRX19 N/A VTRXPAD19 N/A RXNPAD19 N/A RXPPAD19 N/A GNDA19 N/A TXPPAD19 N/A TXNPAD19 N/A VTTXPAD19 N/A AVCCAUXTX19 N/A AVCCAUXRX21 N/A VTRXPAD21 N/A RXNPAD21 N/A RXPPAD21 ...

  • Page 155

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND ...

  • Page 156

    R Table 6: FG456/FGG456 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND ...

  • Page 157

    R FG456/FGG456 Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 2: FG456/FGG456 Fine-Pitch BGA Package Specifications DS083 (v4.7) November 5, 2007 Product Specification Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information www.xilinx.com Module ...

  • Page 158

    R FG676/FGG676 Fine-Pitch BGA Package As shown in Table 7, XC2VP20, XC2VP30, and XC2VP40 Virtex-II Pro devices are available in the FG676/FGG676 fine-pitch BGA package. The pins in these devices are the same, except for the differences shown in the ...

  • Page 159

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 0 IO_L55N_0 0 IO_L55P_0 0 IO_L57N_0 0 IO_L57P_0/VREF_0 0 IO_L67N_0 0 IO_L67P_0 0 IO_L69N_0 0 IO_L69P_0/VREF_0 0 IO_L74N_0/GCLK7P 0 IO_L74P_0/GCLK6S 0 IO_L75N_0/GCLK5P 0 IO_L75P_0/GCLK4S 1 IO_L75N_1/GCLK3P 1 IO_L75P_1/GCLK2S ...

  • Page 160

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 1 IO_L45N_1/VREF_1 1 IO_L45P_1 1 IO_L43N_1 1 IO_L43P_1 1 IO_L39N_1 1 IO_L39P_1 1 IO_L37N_1 1 IO_L37P_1 1 IO_L09N_1/VREF_1 1 IO_L09P_1 1 IO_L07N_1 1 IO_L07P_1 1 IO_L06N_1 1 IO_L06P_1 ...

  • Page 161

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 2 IO_L31P_2 2 IO_L32N_2 2 IO_L32P_2 2 IO_L34N_2/VREF_2 2 IO_L34P_2 2 IO_L36N_2 2 IO_L36P_2 2 IO_L37N_2 2 IO_L37P_2 2 IO_L38N_2 2 IO_L38P_2 2 IO_L40N_2/VREF_2 2 IO_L40P_2 2 IO_L42N_2 ...

  • Page 162

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 2 IO_L58N_2/VREF_2 2 IO_L58P_2 2 IO_L60N_2 2 IO_L60P_2 2 IO_L85N_2 2 IO_L85P_2 2 IO_L86N_2 2 IO_L86P_2 2 IO_L88N_2/VREF_2 2 IO_L88P_2 2 IO_L90N_2 2 IO_L90P_2 3 IO_L90N_3 3 IO_L90P_3 ...

  • Page 163

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 3 IO_L49N_3 3 IO_L49P_3 3 IO_L48N_3 3 IO_L48P_3 3 IO_L47N_3 3 IO_L47P_3 3 IO_L45N_3/VREF_3 3 IO_L45P_3 3 IO_L43N_3 3 IO_L43P_3 3 IO_L42N_3 3 IO_L42P_3 3 IO_L41N_3 3 IO_L41P_3 ...

  • Page 164

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 3 IO_L03P_3 3 IO_L02N_3 3 IO_L02P_3 3 IO_L01N_3/VRP_3 3 IO_L01P_3/VRN_3 4 IO_L01N_4/BUSY/DOUT 4 IO_L01P_4/INIT_B 4 IO_L02N_4/D0/DIN 4 IO_L02P_4/D1 4 IO_L03N_4/D2 4 IO_L03P_4/D3 4 IO_L05_4/No_Pair 4 IO_L06N_4/VRP_4 4 IO_L06P_4/VRN_4 ...

  • Page 165

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 4 IO_L54N_4 4 IO_L54P_4 4 IO_L55N_4 4 IO_L55P_4 4 IO_L57N_4 4 IO_L57P_4/VREF_4 4 IO_L67N_4 4 IO_L67P_4 4 IO_L69N_4 4 IO_L69P_4/VREF_4 4 IO_L74N_4/GCLK3S 4 IO_L74P_4/GCLK2P 4 IO_L75N_4/GCLK1S 4 IO_L75P_4/GCLK0P ...

  • Page 166

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 5 IO_L46N_5 5 IO_L46P_5 5 IO_L45N_5/VREF_5 5 IO_L45P_5 5 IO_L43N_5 5 IO_L43P_5 5 IO_L39N_5 5 IO_L39P_5 5 IO_L37N_5 5 IO_L37P_5 5 IO_L09N_5/VREF_5 5 IO_L09P_5 5 IO_L07N_5/VREF_5 5 IO_L07P_5 ...

  • Page 167

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 6 IO_L23N_6 6 IO_L24P_6 6 IO_L24N_6 6 IO_L31P_6 6 IO_L31N_6 6 IO_L33P_6 6 IO_L33N_6/VREF_6 6 IO_L35P_6 6 IO_L35N_6 6 IO_L36P_6 6 IO_L36N_6 6 IO_L37P_6 6 IO_L37N_6 6 IO_L39P_6 ...

  • Page 168

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 6 IO_L55P_6 6 IO_L55N_6 6 IO_L57P_6 6 IO_L57N_6/VREF_6 6 IO_L59P_6 6 IO_L59N_6 6 IO_L60P_6 6 IO_L60N_6 6 IO_L85P_6 6 IO_L85N_6 6 IO_L87P_6 6 IO_L87N_6/VREF_6 6 IO_L89P_6 6 IO_L89N_6 ...

  • Page 169

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 7 IO_L52P_7 7 IO_L52N_7/VREF_7 7 IO_L50P_7 7 IO_L50N_7 7 IO_L49P_7 7 IO_L49N_7 7 IO_L48P_7 7 IO_L48N_7 7 IO_L46P_7 7 IO_L46N_7/VREF_7 7 IO_L44P_7 7 IO_L44N_7 7 IO_L43P_7 7 IO_L43N_7 ...

  • Page 170

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 7 IO_L04N_7/VREF_7 7 IO_L03P_7 7 IO_L03N_7 7 IO_L02P_7 7 IO_L02N_7 7 IO_L01P_7/VRN_7 7 IO_L01N_7/VRP_7 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 ...

  • Page 171

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description 3 VCCO_3 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 5 VCCO_5 5 VCCO_5 5 VCCO_5 5 VCCO_5 5 VCCO_5 5 VCCO_5 ...

  • Page 172

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description N/A VTTXPAD4 N/A TXNPAD4 N/A TXPPAD4 N/A GNDA4 N/A RXPPAD4 N/A RXNPAD4 N/A VTRXPAD4 N/A AVCCAUXRX4 N/A AVCCAUXTX6 N/A VTTXPAD6 N/A TXNPAD6 N/A TXPPAD6 N/A GNDA6 N/A RXPPAD6 ...

  • Page 173

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description N/A RSVD N/A VBATT N/A TMS N/A TCK N/A TDO N/A CCLK N/A PWRDWN_B N/A DONE N/A AVCCAUXRX16 N/A VTRXPAD16 N/A RXNPAD16 N/A RXPPAD16 N/A GNDA16 N/A TXPPAD16 ...

  • Page 174

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description N/A AVCCAUXRX21 N/A VTRXPAD21 N/A RXNPAD21 N/A RXPPAD21 N/A GNDA21 N/A TXPPAD21 N/A TXNPAD21 N/A VTTXPAD21 N/A AVCCAUXTX21 N/A M2 N/A M0 N/A M1 N/A TDI N/A VCCINT ...

  • Page 175

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCAUX N/A VCCAUX N/A VCCAUX ...

  • Page 176

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND ...

  • Page 177

    R Table 7: FG676/FGG676 — XC2VP20, XC2VP30, and XC2VP40 Bank Pin Description N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND ...

  • Page 178

    R FG676/FGG676 Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 3: FG676/FGG676 Fine-Pitch BGA Package Specifications DS083 (v4.7) November 5, 2007 Product Specification Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information www.xilinx.com Module ...

  • Page 179

    R FF672 Flip-Chip Fine-Pitch BGA Package As shown in Table 8, XC2VP2, XC2VP4, and XC2VP7 Virtex-II Pro devices are available in the FF672 flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for differences shown ...

  • Page 180

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 0 IO_L73N_0 0 IO_L73P_0 0 IO_L74N_0/GCLK7P 0 IO_L74P_0/GCLK6S 0 IO_L75N_0/GCLK5P 0 IO_L75P_0/GCLK4S 1 IO_L75N_1/GCLK3P 1 IO_L75P_1/GCLK2S 1 IO_L74N_1/GCLK1P 1 IO_L74P_1/GCLK0S 1 IO_L73N_1 1 IO_L73P_1 1 IO_L69N_1/VREF_1 1 IO_L69P_1 ...

  • Page 181

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 1 IO_L06N_1 1 IO_L06P_1 1 IO_L05_1/No_Pair 1 IO_L03N_1/VREF_1 1 IO_L03P_1 1 IO_L02N_1 1 IO_L02P_1 1 IO_L01N_1/VRP_1 1 IO_L01P_1/VRN_1 2 IO_L01N_2/VRP_2 2 IO_L01P_2/VRN_2 2 IO_L02N_2 2 IO_L02P_2 2 IO_L03N_2 ...

  • Page 182

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 2 IO_L48P_2 2 IO_L49N_2 2 IO_L49P_2 2 IO_L50N_2 2 IO_L50P_2 2 IO_L51N_2 2 IO_L51P_2 2 IO_L52N_2/VREF_2 2 IO_L52P_2 2 IO_L53N_2 2 IO_L53P_2 2 IO_L54N_2 2 IO_L54P_2 2 IO_L55N_2 ...

  • Page 183

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 3 IO_L90N_3 3 IO_L90P_3 3 IO_L89N_3 3 IO_L89P_3 3 IO_L88N_3 3 IO_L88P_3 3 IO_L87N_3/VREF_3 3 IO_L87P_3 3 IO_L86N_3 3 IO_L86P_3 3 IO_L85N_3 3 IO_L85P_3 3 IO_L60N_3 3 IO_L60P_3 ...

  • Page 184

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 3 IO_L48N_3 3 IO_L48P_3 3 IO_L47N_3 3 IO_L47P_3 3 IO_L46N_3 3 IO_L46P_3 3 IO_L45N_3/VREF_3 3 IO_L45P_3 3 IO_L44N_3 3 IO_L44P_3 3 IO_L43N_3 3 IO_L43P_3 3 IO_L42N_3 3 IO_L42P_3 ...

  • Page 185

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 4 IO_L05_4/No_Pair 4 IO_L06N_4/VRP_4 4 IO_L06P_4/VRN_4 4 IO_L07N_4 4 IO_L07P_4/VREF_4 4 IO_L08N_4 4 IO_L08P_4 4 IO_L09N_4 4 IO_L09P_4/VREF_4 4 IO_L37N_4 4 IO_L37P_4 4 IO_L38N_4 4 IO_L38P_4 4 IO_L39N_4 ...

  • Page 186

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 5 IO_L74P_5/GCLK4P 5 IO_L73N_5 5 IO_L73P_5 5 IO_L69N_5/VREF_5 5 IO_L69P_5 5 IO_L68N_5 5 IO_L68P_5 5 IO_L67N_5 5 IO_L67P_5 5 IO_L45N_5/VREF_5 5 IO_L45P_5 5 IO_L44N_5 5 IO_L44P_5 5 IO_L43N_5 ...

  • Page 187

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 6 IO_L01P_6/VRN_6 6 IO_L01N_6/VRP_6 6 IO_L02P_6 6 IO_L02N_6 6 IO_L03P_6 6 IO_L03N_6/VREF_6 6 IO_L04P_6 6 IO_L04N_6 6 IO_L05P_6 6 IO_L05N_6 6 IO_L06P_6 6 IO_L06N_6 6 IO_L39P_6 6 IO_L39N_6/VREF_6 ...

  • Page 188

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 6 IO_L52N_6 6 IO_L53P_6 6 IO_L53N_6 6 IO_L54P_6 6 IO_L54N_6 6 IO_L55P_6 6 IO_L55N_6 6 IO_L56P_6 6 IO_L56N_6 6 IO_L57P_6 6 IO_L57N_6/VREF_6 6 IO_L58P_6 6 IO_L58N_6 6 IO_L59P_6 ...

  • Page 189

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 7 IO_L87N_7 7 IO_L86P_7 7 IO_L86N_7 7 IO_L85P_7 7 IO_L85N_7 7 IO_L60P_7 7 IO_L60N_7 7 IO_L59P_7 7 IO_L59N_7 7 IO_L58P_7 7 IO_L58N_7/VREF_7 7 IO_L57P_7 7 IO_L57N_7 7 IO_L56P_7 ...

  • Page 190

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 7 IO_L44P_7 7 IO_L44N_7 7 IO_L43P_7 7 IO_L43N_7 7 IO_L42P_7 7 IO_L42N_7 7 IO_L40P_7 7 IO_L40N_7/VREF_7 7 IO_L06P_7 7 IO_L06N_7 7 IO_L05P_7 7 IO_L05N_7 7 IO_L04P_7 7 IO_L04N_7/VREF_7 ...

  • Page 191

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 4 VCCO_4 4 VCCO_4 ...

  • Page 192

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description 7 VCCO_7 7 VCCO_7 7 VCCO_7 N/A CCLK N/A PROG_B N/A DONE N/A M0 N/A M1 N/A M2 N/A TCK N/A TDI N/A TDO N/A TMS N/A PWRDWN_B ...

  • Page 193

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description N/A AVCCAUXRX9 N/A AVCCAUXRX16 N/A VTRXPAD16 N/A RXNPAD16 N/A RXPPAD16 N/A GNDA16 N/A TXPPAD16 N/A TXNPAD16 N/A VTTXPAD16 N/A AVCCAUXTX16 N/A AVCCAUXRX18 N/A VTRXPAD18 N/A RXNPAD18 N/A RXPPAD18 ...

  • Page 194

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description N/A AVCCAUXRX19 N/A VTRXPAD19 N/A RXNPAD19 N/A RXPPAD19 N/A GNDA19 N/A TXPPAD19 N/A TXNPAD19 N/A VTTXPAD19 N/A AVCCAUXTX19 N/A AVCCAUXRX21 N/A VTRXPAD21 N/A RXNPAD21 N/A RXPPAD21 N/A GNDA21 ...

  • Page 195

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCINT N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX N/A VCCAUX ...

  • Page 196

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND ...

  • Page 197

    R Table 8: FF672 — XC2VP2, XC2VP4, and XC2VP7 Bank Pin Description N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND ...

  • Page 198

    R FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 4: FF672 Flip-Chip Fine-Pitch BGA Package Specifications FF896 Flip-Chip Fine-Pitch BGA Package As shown in Table 9, XC2VP7, XC2VP20, and XC2VP30 Virtex-II Pro devices are available in the FF896 flip-chip ...

  • Page 199

    R Table 9: FF896 — XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank Virtex-II Pro devices 0 IO_L01N_0/VRP_0 0 IO_L01P_0/VRN_0 0 IO_L02N_0 0 IO_L02P_0 0 IO_L03N_0 0 IO_L03P_0/VREF_0 0 IO_L05_0/No_Pair 0 IO_L06N_0 0 IO_L06P_0 0 IO_L07N_0 0 IO_L07P_0 0 IO_L08N_0 ...

  • Page 200

    R Table 9: FF896 — XC2VP7, XC2VP20, XC2VPX20, and XC2VP30 Pin Description Bank Virtex-II Pro devices 0 IO_L53_0/No_Pair 0 IO_L54N_0 0 IO_L54P_0 0 IO_L56N_0 0 IO_L56P_0 0 IO_L57N_0 0 IO_L57P_0/VREF_0 0 IO_L67N_0 0 IO_L67P_0 0 IO_L68N_0 0 IO_L68P_0 0 IO_L69N_0 ...