NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 770

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NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
21.1.5
BBAR—BIOS Base Address Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 50h
Default Value:
00000000h
Bit
31:24
Reserved.
Bottom of System Flash — R/W. This field determines the bottom of the System
BIOS. The Intel
address field is less than this value. This field corresponds to bits 23:8 of the 3-byte
address; bits 7:0 are assumed to be 00h for this vector when comparing to a potential
SPI address.
23:8
NOTE: Software must always program 1s into the upper, Don’t Care, bits of this field
based on the flash size. Hardware does not know the size of the flash array and
relies upon the correct programming by software. The default value of 0000h
results in all cycles allowed.
NOTE: In the event that this value is programmed below some of the BIOS Memory
segments, described above, this protection policy takes precedence.
7:0
Reserved
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15)
is set.
21.1.6
PREOP—Prefix Opcode Configuration Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 54h
Default Value:
0004h
Bit
Prefix Opcode 1— R/W. Software programs an SPI opcode into this field that is
15:8
permitted to run as the first command in an atomic cycle sequence.
Prefix Opcode 0 — R/W. Software programs an SPI opcode into this field that is
7:0
permitted to run as the first command in an atomic cycle sequence.
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15)
is set.
770
Serial Peripheral Interface (SPI) (Desktop and Mobile Only)
Attribute:
Size:
Description
®
ICH7 will not run programmed commands nor memory reads whose
Attribute:
Size:
Description
R/W
32 bits
R/W
16 bits
®
Intel
ICH7 Family Datasheet

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