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NH82801GBM SL8YB

NH82801GBM SL8YB | |
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Manufacturer Part Number | NH82801GBM SL8YB |
Manufacturer | Intel Corporation |
NH82801GBM SL8YB datasheet |
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Specifications of NH82801GBM SL8YB | |||
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Case | BGA | Date_code | 07+ |
PrevNext
11.
Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset
HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be
Running.
12.
GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset
13.
GPIO25 transitions from pulled high internally to actively driven within 100 ms of the
deassertion of the RSMRST# pin.
3.4
Power Planes for Input Signals
Table 3-5
and
Table 3-6
well as what device drives the signal at various times. Valid states include:
High
Low
Static: Will be high or low, but will not change
Driven: Will be high or low, and is allowed to change
Running: For input clocks
ICH7 suspend well signal states are indeterminate and undefined and may glitch prior
to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4# and
SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion.
ICH7 core well signal states are indeterminate and undefined and may glitch prior to
PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are
determinate and defined prior to PWROK assertion.
Table 3-5.
Power Plane for Input Signals for Desktop Only Configurations (Sheet 1 of 3)
Signal Name
A20GATE
ACZ_BIT_CLK
(AC ‘97 Mode)
ACZ_SDIN[2:0] (AC ‘97
Mode)
ACZ_SDIN[2:0] (Intel®
High Definition Audio
Mode)
CLK14
CLK48
DDREQ
DMI_CLKP, DMI_CLKN
EE_DIN
FERR#
PERp[4:1], PERn[4:1]
PERp[6:5], PERn[6:5]
®
(Intel
ICH7R and
ICH7DH Only)
DMI[3:0]RXP,
DMI[3:0]RXN
IDEIRQ
INTRUDER#
90
show the power plane associated with each input signal, as
Power Well
Driver During Reset
External
Core
Microcontroller
Core
AC ’97 Codec
Suspend
AC ’97 Codec
Intel® High Definition
Suspend
Audio Codec
Core
Clock Generator
Core
Clock Generator
Core
IDE Device
Core
Clock Generator
Suspend
EEPROM Component
Core
Processor
Core
PCI Express* Device
Core
(G)MCH
Core
IDE
RTC
External Switch
®
Intel
ICH7 Pin States
1
S1
S3
S4/S5
COLD
Static
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Running
Low
Low
Running
Low
Low
Static
Low
Low
Running
Low
Low
Driven
Driven
Driven
Static
Low
Low
Driven
Driven
Driven
Driven
Low
Low
Static
Low
Low
Driven
Driven
Driven
®
Intel
ICH7 Family Datasheet
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