ISPLSI1048E50LQI Lattice Semiconductor Corp., ISPLSI1048E50LQI Datasheet

ISPLSI1048E50LQI

Manufacturer Part Number

ISPLSI1048E50LQI

Description

QFP

Manufacturer

Lattice Semiconductor Corp.

Datasheets

1.ISPLSI1048E100LT.pdf (17 pages)

2.ISPLSI1016E100LT44.pdf (17 pages)

Specifications of ISPLSI1048E50LQI

Date_code

07+

Current page: 1 of 17
Download datasheet (288Kb)

• HIGH DENSITY PROGRAMMABLE LOGIC

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

1048e_12

Features

— 8,000 PLD Gates

— 96 I/O Pins, Twelve Dedicated Inputs

— 288 Registers

— High-Speed Global Interconnects

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

— Functionally and Pin-out Compatible to ispLSI 1048C

—

— TTL Compatible Inputs and Outputs

— Electrically Eraseable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

— Complete Programmable Device Can Combine Glue

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

— Lead-Free Package Options

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

Machines, Address Decoders, etc.

Market and Improved Product Quality

Logic and Structured Designs

Minimize Switching Noise

Interconnectivity

max = 125 MHz Maximum Operating Frequency

pd = 7.5 ns Propagation Delay

CMOS

TECHNOLOGY

In-System Programmable High Density PLD

The ispLSI 1048E is a High Density Programmable Logic

Device containing 288 Registers, 96 Universal I/O pins,

12 Dedicated Input pins, four Dedicated Clock Input pins,

two dedicated Global OE input pins, and a Global Routing

Pool (GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 1048E offers

5V non-volatile in-system programmability of the logic, as

well as the interconnect to provide truly reconfigurable

systems. A functional superset of the ispLSI 1048 archi-

tecture, the ispLSI 1048E device adds two new global

output enable pins and two additional dedicated inputs.

The basic unit of logic on the ispLSI 1048E device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…F7 (see Figure 1). There are a total of 48 GLBs in the

ispLSI 1048E device. Each GLB has 18 inputs, a pro-

grammable AND/OR/Exclusive OR array, and four outputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

Functional Block Diagram

Description

F7 F6 F5 F4 F3 F2 F1 F0

B0 B1 B2 B3 B4 B5 B6 B7

Global Routing Pool (GRP)

Output Routing Pool

ispLSI

E7 E6 E5 E4 E3 E2 E1 E0

C0 C1 C2 C3 C4 C5 C6 C7

Logic

Array

Output Routing Pool

D Q

1048E

GLB

August 2006

CLK

0139G1A-isp

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