ISPLSI2096A80LT128I Lattice Semiconductor Corp., ISPLSI2096A80LT128I Datasheet

ISPLSI2096A80LT128I

Manufacturer Part Number

ISPLSI2096A80LT128I

Description

QFP128

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI2096.80LQ.pdf (12 pages)

Specifications of ISPLSI2096A80LT128I

Date_code

04+

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• ENHANCEMENTS

• HIGH DENSITY PROGRAMMABLE LOGIC

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

2096_09

Features

— 4000 PLD Gates

— 96 I/O Pins, Six Dedicated Inputs

— 96 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

— Complete Programmable Device Can Combine

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

— Lead-Free Package Options

— ispLSI 2096A is Fully Form and Function Compatible

— ispLSI 2096A is Built on an Advanced 0.35 Micron

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

Machines, Address Decoders, etc.

Market and Improved Product Quality

Glue Logic and Structured Designs

Minimize Switching Noise

Interconnectivity

to the ispLSI 2096, with Identical Timing

Specifcations and Packaging

max = 125 MHz Maximum Operating Frequency

pd = 7.5 ns Propagation Delay

CMOS

Technology

CMOS

TECHNOLOGY

In-System Programmable High Density PLD

The ispLSI 2096 and 2096A are High Density Program-

mable Logic Devices. The devices contain 96 Registers,

96 Universal I/O pins, six Dedicated Input pins, three

Dedicated Clock Input pins, two dedicated Global OE

input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 2096 and 2096A feature 5V in-

system programmability and in-system diagnostic

capabilities. The ispLSI 2096 and 2096A offer non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

The basic unit of logic on these devices is the Generic

Logic Block (GLB). The GLBs are labeled A0, A1…C7

(Figure 1). There are a total of 24 GLBs in the ispLSI 2096

and 2096A devices. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

Functional Block Diagram

Description

Output Routing Pool (ORP)

GLB

Logic

Array

ispLSI

D Q

Global Routing Pool

Output Routing Pool (ORP)

(GRP)

2096/A

August 2006

0919/2096

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