M30626FJPFPU5C

Manufacturer Part NumberM30626FJPFPU5C
DescriptionQFP-100
ManufacturerRenesas Electronics Corporation.
M30626FJPFPU5C datasheet
 


Specifications of M30626FJPFPU5C

Date_code10+  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
Page 271
272
Page 272
273
Page 273
274
Page 274
275
Page 275
276
Page 276
277
Page 277
278
Page 278
279
Page 279
280
Page 280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
Page 275/308

Download datasheet (2Mb)Embed
PrevNext
Chapter 5
Interrupt
The register save operation performed in an interrupt sequence differs depending on whether the con-
tent of the stack pointer (SP)
*1
If the stack pointer (SP)
indicates an even number, the contents of the flag register (FLG) and program
counter (PC) each are saved simultaneously all 16 bits together. If the stack pointer indicates an odd
number, the register contents each are saved in two operations 8 bits at a time. Figure 5.3.3 shows how
registers are saved in each case.
*1 Stack pointer indicated by the U flag.
(1) When stack pointer (SP) contains an even number
Address
Stack area
[SP]–5
(Odd address)
[SP]–4
Program counter (PC
)
L
(Even address)
[SP]–3
Program counter (PC
)
M
(Odd address)
[SP]–2
Flag register (FLG
)
(Even address)
L
[SP]–1
Flag register
Program counter
(PC
)
(Odd address)
(FLG
)
H
H
[SP]
(Even address)
[SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
*
After the microcomputer finishes saving registers, the SP content is [SP] minus 4.
Figure 5.3.3 Operations to save registers
*1
is an even or an odd number when an interrupt request is acknowledged.
(2) When stack pointer (SP) contains an odd number
Sequence in which order
Address
registers are saved
[SP]–5
(Even address)
[SP]–4
(Odd address)
(2) Saved simul-
[SP]–3
taneously, all 16
(Even address)
bits together
[SP]–2
(1) Saved simul-
(Odd address)
taneously, all 16
[SP]–1
(Even address)
bits together
[SP]
(Odd address)
Finished saving registers
in two operations.
257
5.3 Interrupt Sequence
Stack area
Sequence in which order
registers are saved
Program counter (PC
)
L
(3)
Program counter (PC
)
(4)
M
Saved
separately, 8
(1)
Flag register (FLG
)
L
bits at a time
Flag register
(2)
Program counter
(FLG
)
(PC
)
H
H
Finished saving registers in
four operations.