M30626FJPFPU5C

Manufacturer Part NumberM30626FJPFPU5C
DescriptionQFP-100
ManufacturerRenesas Electronics Corporation.
M30626FJPFPU5C datasheet
 


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Chapter 5
Interrupt
The register save operation performed in an interrupt sequence differs depending on whether the con-
tent of the stack pointer (SP)
*1
If the stack pointer (SP)
indicates an even number, the contents of the flag register (FLG) and program
counter (PC) each are saved simultaneously all 16 bits together. If the stack pointer indicates an odd
number, the register contents each are saved in two operations 8 bits at a time. Figure 5.3.3 shows how
registers are saved in each case.
*1 Stack pointer indicated by the U flag.
(1) When stack pointer (SP) contains an even number
Address
Stack area
[SP]–5
(Odd address)
[SP]–4
Program counter (PC
)
L
(Even address)
[SP]–3
Program counter (PC
)
M
(Odd address)
[SP]–2
Flag register (FLG
)
(Even address)
L
[SP]–1
Flag register
Program counter
(PC
)
(Odd address)
(FLG
)
H
H
[SP]
(Even address)
[SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
*
After the microcomputer finishes saving registers, the SP content is [SP] minus 4.
Figure 5.3.3 Operations to save registers
*1
is an even or an odd number when an interrupt request is acknowledged.
(2) When stack pointer (SP) contains an odd number
Sequence in which order
Address
registers are saved
[SP]–5
(Even address)
[SP]–4
(Odd address)
(2) Saved simul-
[SP]–3
taneously, all 16
(Even address)
bits together
[SP]–2
(1) Saved simul-
(Odd address)
taneously, all 16
[SP]–1
(Even address)
bits together
[SP]
(Odd address)
Finished saving registers
in two operations.
257
5.3 Interrupt Sequence
Stack area
Sequence in which order
registers are saved
Program counter (PC
)
L
(3)
Program counter (PC
)
(4)
M
Saved
separately, 8
(1)
Flag register (FLG
)
L
bits at a time
Flag register
(2)
Program counter
(FLG
)
(PC
)
H
H
Finished saving registers in
four operations.

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