S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 


Specifications of S3C44B0X

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S3C2400 RISC MICROPROCESSOR
MULTI-MASTER IIC-BUS CONTROL/STATUS REGISTER (IICSTAT)
Register
Address
IICSTAT
0x15400004
IICSTAT
Bit
Mode selection
[7:6]
IIC-bus master/slave Tx/Rx mode select bits:
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Busy signal
[5]
IIC-Bus busy signal status bit:
status /
0 = read) IIC-bus not busy. (IIC always senses BUS
START STOP
condition
1 = read) IIC-bus busy
Serial output
[4]
IIC-bus data output enable/disable bit:
enable
0=Disable Rx/Tx,
Arbitration status
[3]
IIC-bus arbitration procedure status flag bit:
flag
0 = Bus arbitration successful
1 = Bus arbitration failed during serial I/O
Address-as-slave
[2]
IIC-bus address-as-slave status flag bit:
status flag
0 = cleared when START/STOP condition was
1 = Received slave address matches the address
Address zero
[1]
IIC-bus address zero status flag bit:
status flag
0 = cleared when START/STOP condition was
1 = Received slave address is 00000000b
Last-received bit
[0]
IIC-bus last-received bit status flag bit
status flag
0 = Last-received bit is 0 (ACK was received).
1 = Last-receive bit is 1 (ACK was not received).
R/W
Description
R/W
IIC-Bus control/status register
Description
start/stop condition.)
write) IIC-bus STOP signal generation
write) IIC-bus START signal generation.
The data in IICDS will be transferred
automatically just after the start signal.
Also, the delay to check the start condition
is inserted automatically.
1=Enable Rx/Tx
detected.
value in the IICADD.
detected at the SDA/SCL line.
IIC-BUS INTERFACE
Reset Value
0000_0000
Initial State
0
0
0
0
0
0
0
20-12