ADSP-2183-KST-210 Analog Devices, ADSP-2183-KST-210 Datasheet

ADSP-2183-KST-210

Manufacturer Part Number

ADSP-2183-KST-210

Description

Manufacturer

Analog Devices

Datasheet

1.ADSP2183KST210.pdf (31 pages)

Specifications of ADSP-2183-KST-210

Case

QFP-128

Date_code

9931

Current page: 1 of 31
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ICE-Port is a trademark of Analog Devices, Inc.

GENERAL DESCRIPTION

The ADSP-2183 is a single-chip microcomputer optimized for

digital signal processing (DSP) and other high speed numeric

processing applications.

The ADSP-2183 combines the ADSP-2100 family base architec-

ture (three computational units, data address generators and

a program sequencer) with two serial ports, a 16-bit internal

DMA port, a byte DMA port, a programmable timer, Flag I/O,

extensive interrupt capabilities, and on-chip program and

data memory.

The ADSP-2183 integrates 80K bytes of on-chip memory con-

figured as 16K words (24-bit) of program RAM, and 16K words

(16-bit) of data RAM. Power-down circuitry is also provided to

meet the low power needs of battery operated portable equipment.

The ADSP-2183 is available in 128-lead LQFP, and 144-Ball

Mini-BGA packages.

In addition, the ADSP-2183 supports new instructions, which

include bit manipulations—bit set, bit clear, bit toggle, bit test—

new ALU constants, new multiplication instruction (x squared),

biased rounding, result free ALU operations, I/O memory trans-

fers and global interrupt masking, for increased flexibility.

Fabricated in a high speed, double metal, low power, CMOS

process, the ADSP-2183 operates with a 19 ns instruction cycle

time. Every instruction can execute in a single processor cycle.

The ADSP-2183’s flexible architecture and comprehensive

instruction set allow the processor to perform multiple opera-

tions in parallel. In one processor cycle the ADSP-2183 can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

DATA ADDRESS

GENERATORS

DAG 1

ALU

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

DAG 2

MAC

FUNCTIONAL BLOCK DIAGRAM

SHIFTER

SEQUENCER

PROGRAM

DATA MEMORY DATA

PROGRAM MEMORY DATA

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

DSP Microcomputer

SPORT 0

SERIAL PORTS

PROGRAM

MEMORY

POWERDOWN

SPORT 1

CONTROL

MEMORY

ADSP-2183

DATA

TIMER

PROGRAMMABLE

CONTROLLER

BYTE DMA

FLAGS

INTERNAL

I/O

PORT

DMA

EXTERNAL

ADDRESS

EXTERNAL

DMA

BUS

DATA

BUS

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